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We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

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SMTS SILICON DESIGN ENGINEER

THE ROLE:

The scoping of FEINT expert includes synthesis, formality check, low power check and full-chip SDC generation. AMD design is big and complex with advanced process and technology. FEINT expert needs have rich experience in each domain, control execution risk and lead team to do high quality release on schedule. The member needs co-work with IP/DFT/PD teams, highlights critical issues and makes decisions to make project execution smoothly.

THE PERSON:

• > 8 years working experience on ASIC Implementation
• Knowledgeable in all aspects of ASIC design flow
• Familiar with FEINT EDA tools
• Good leadership skills
• Good teamwork and script skills
• Good training skills to ramp-up new team members

KEY RESPONSIBILITIES:

• Do working assignment for team members, tracking and supporting for critical problems
• Co-work with IP/DFT/PD team to improve timing/area/power during synthesize
• Netlist quality check including EQV/LowPower/Timing
• Generate full-chip level SDC and SDC quality check

PREFERRED EXPERIENCE:

• Synthesize experience by DC/DC-NXT/Fusion-Compiler
• EQV debug experience by FM/LEC
• Low power check experience by VC-LP
• Static Timing Analysis experience by PT
• Power Analysis experience by PTPX
• Good at scripts, like Python/perl/Tcl/Shell

ACADEMIC CREDENTIALS:

• Master in Electrical Engineering or related technical areas

LOCATION:

Shanghai

#LI-VC1

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

SMTS SILICON DESIGN ENGINEER

THE ROLE:

The scoping of FEINT expert includes synthesis, formality check, low power check and full-chip SDC generation. AMD design is big and complex with advanced process and technology. FEINT expert needs have rich experience in each domain, control execution risk and lead team to do high quality release on schedule. The member needs co-work with IP/DFT/PD teams, highlights critical issues and makes decisions to make project execution smoothly.

THE PERSON:

• > 8 years working experience on ASIC Implementation
• Knowledgeable in all aspects of ASIC design flow
• Familiar with FEINT EDA tools
• Good leadership skills
• Good teamwork and script skills
• Good training skills to ramp-up new team members

KEY RESPONSIBILITIES:

• Do working assignment for team members, tracking and supporting for critical problems
• Co-work with IP/DFT/PD team to improve timing/area/power during synthesize
• Netlist quality check including EQV/LowPower/Timing
• Generate full-chip level SDC and SDC quality check

PREFERRED EXPERIENCE:

• Synthesize experience by DC/DC-NXT/Fusion-Compiler
• EQV debug experience by FM/LEC
• Low power check experience by VC-LP
• Static Timing Analysis experience by PT
• Power Analysis experience by PTPX
• Good at scripts, like Python/perl/Tcl/Shell

ACADEMIC CREDENTIALS:

• Master in Electrical Engineering or related technical areas

LOCATION:

Shanghai

#LI-VC1