Hyderabad, India
Not specified
Intermediate
Office work
WHAT YOU DO AT AMD CHANGES EVERYTHING
We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.
AMD together we advance_
SMTS SILICON DESIGN ENGINEER
THE ROLE:
The focus of this role is to plan and execute the front end implementation of IPs and its closure. This involves ownership of synthesis, LEC, CLP, prelayout STA and postlayout STA/Timing closure. Co-ordinate with design team and PNR teams. Guide team members on tenchical issues.
KEY RESPONSIBILITIES:
- Responsible for front end implementation of IPs which includes synthesis, LEC, CLP, prelayout STA and postlayout STA/Timing closure
- Collaborate with designer and PNR teams to achieve closure.
- Understand duration required, plan and execute as per schedule.
- Complete quality delivery for synthesis and timing closure.
- Debug and resolve technical issues
PREFERRED EXPERIENCE:
- Highly experienced in synthesis, LEC, CLP and timing closure
- Prefered top level or SOC level experience
- Have handled blocks with complex designs, high frequency clocks and complex clocking
- complete understanding of timing constraints, low power aspects and concepts of DFT
- Have debug experience to solve issues.
- scripting and automation
ACADEMIC CREDENTIALS:
- Bachelors with 8 years of experience or Masters degree with 6 years of experience in Electrical Engineering
#LI-RP1
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
SMTS SILICON DESIGN ENGINEER
THE ROLE:
The focus of this role is to plan and execute the front end implementation of IPs and its closure. This involves ownership of synthesis, LEC, CLP, prelayout STA and postlayout STA/Timing closure. Co-ordinate with design team and PNR teams. Guide team members on tenchical issues.
KEY RESPONSIBILITIES:
- Responsible for front end implementation of IPs which includes synthesis, LEC, CLP, prelayout STA and postlayout STA/Timing closure
- Collaborate with designer and PNR teams to achieve closure.
- Understand duration required, plan and execute as per schedule.
- Complete quality delivery for synthesis and timing closure.
- Debug and resolve technical issues
PREFERRED EXPERIENCE:
- Highly experienced in synthesis, LEC, CLP and timing closure
- Prefered top level or SOC level experience
- Have handled blocks with complex designs, high frequency clocks and complex clocking
- complete understanding of timing constraints, low power aspects and concepts of DFT
- Have debug experience to solve issues.
- scripting and automation
ACADEMIC CREDENTIALS:
- Bachelors with 8 years of experience or Masters degree with 6 years of experience in Electrical Engineering
#LI-RP1
