WHAT YOU DO AT AMD CHANGES EVERYTHING
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SMTS SILICON DESIGN ENGINEER
THE ROLE:
AMD Strategic Silicon Solutions group is well regarded to deliver best semi-custom silicon solutions to customers. As part of its SOC Physical Verification team, you will be an integral part of ensuring our latest silicon design compliance with the stringent leading-edge technology physical and electrical requirements in good engineering practice.
THE PERSON:
The candidate will work in a team led by industry-leading experts in the field, with a strong culture of collaboration, accountability, respect of innovation, and drive for mutual success, with exposure to vast variety of ASCII designs, and will work closely with Fellows, Principal Engineers, Architects, Technology/CAD, IP and other design teams to plan, implement and signoff our many exciting silicon solutions. The candidate should be highly accurate and detail-oriented, possessing excellent communication and outstanding problem-solving skills. Must have led physical verification team/s in the capacity of technical lead or as a go to person.
KEY RESPONSIBLITIES:
- Physical Verification:
- Perform SOC LVS/DRC/Antenna/LUP/ESD/DFM plan, check and debug.
- Work with the extended Physical Design team on Floorplan, Macro and RAM placement, bump assignment, ESD planning, APR physical construction flow optimization to achieve clean by construction.
- Show capability in understanding geometrical Boolean operations is a must.
- Hand on experience in custom CMOS layout design is preferred.
- Capable of understanding complex rulecheck definition, identifying critical requirement affecting construction / methodology, knowledge in rule coding, latchup / ESD protection mechanism is highly desirable.
- Accountable for on-time project delivery.
- Contribute towards continuous process improvement.
PREFERRED EXPERIENCE:
- Minimum 13+ years of relevant work experience
- Familiar with Unix/Linux environment and Shell scripting.
- Hands on experience in EDA tools like Calibre, ICV and ICC2 are must for senior position.
- Experience in TCL, Perl or Python coding is preferred.
- Strong problem solving skills demonstrated with good engineering reasoning/judgement.
- Good inter-personal and communication skills are must.
- Dedicated, willing to learn, hardworking and good team player.
- Multiple SOC tapeout experience is must for senior position.
- Knowledge in IREM is highly desirable but optional.
- Hardware skills: An understanding of analog design concepts such as MOS transistor operation and physical characteristics, logic circuit operation.
- Software skills: Ability to develop well-structured and maintainable software. Experience with code testing and regression and their importance.
- Experience in UNIX shell environment, Perl scripting, JavaScript, SQL, HTML, SKILL, spice netlist syntax and simulation are assets.
- Experience in 5nm & below technologies.
ACADEMIC CREDENTIALS:
Bachelors or Master's degree in Computer/Electronics/Electrical Engineering
#LI-SR4
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
SMTS SILICON DESIGN ENGINEER
THE ROLE:
AMD Strategic Silicon Solutions group is well regarded to deliver best semi-custom silicon solutions to customers. As part of its SOC Physical Verification team, you will be an integral part of ensuring our latest silicon design compliance with the stringent leading-edge technology physical and electrical requirements in good engineering practice.
THE PERSON:
The candidate will work in a team led by industry-leading experts in the field, with a strong culture of collaboration, accountability, respect of innovation, and drive for mutual success, with exposure to vast variety of ASCII designs, and will work closely with Fellows, Principal Engineers, Architects, Technology/CAD, IP and other design teams to plan, implement and signoff our many exciting silicon solutions. The candidate should be highly accurate and detail-oriented, possessing excellent communication and outstanding problem-solving skills. Must have led physical verification team/s in the capacity of technical lead or as a go to person.
KEY RESPONSIBLITIES:
- Physical Verification:
- Perform SOC LVS/DRC/Antenna/LUP/ESD/DFM plan, check and debug.
- Work with the extended Physical Design team on Floorplan, Macro and RAM placement, bump assignment, ESD planning, APR physical construction flow optimization to achieve clean by construction.
- Show capability in understanding geometrical Boolean operations is a must.
- Hand on experience in custom CMOS layout design is preferred.
- Capable of understanding complex rulecheck definition, identifying critical requirement affecting construction / methodology, knowledge in rule coding, latchup / ESD protection mechanism is highly desirable.
- Accountable for on-time project delivery.
- Contribute towards continuous process improvement.
PREFERRED EXPERIENCE:
- Minimum 13+ years of relevant work experience
- Familiar with Unix/Linux environment and Shell scripting.
- Hands on experience in EDA tools like Calibre, ICV and ICC2 are must for senior position.
- Experience in TCL, Perl or Python coding is preferred.
- Strong problem solving skills demonstrated with good engineering reasoning/judgement.
- Good inter-personal and communication skills are must.
- Dedicated, willing to learn, hardworking and good team player.
- Multiple SOC tapeout experience is must for senior position.
- Knowledge in IREM is highly desirable but optional.
- Hardware skills: An understanding of analog design concepts such as MOS transistor operation and physical characteristics, logic circuit operation.
- Software skills: Ability to develop well-structured and maintainable software. Experience with code testing and regression and their importance.
- Experience in UNIX shell environment, Perl scripting, JavaScript, SQL, HTML, SKILL, spice netlist syntax and simulation are assets.
- Experience in 5nm & below technologies.
ACADEMIC CREDENTIALS:
Bachelors or Master's degree in Computer/Electronics/Electrical Engineering
#LI-SR4