WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_

SMTS SILICON DESIGN ENGINEER

THE ROLE: 

As a member of the Semi Custom Group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success.

THE PERSON:

A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills.

KEY RESPONSIBLITIES:

• Work closely with SOC Architecture team for SOC clocks statistical timing target goals.
• Responsible for merging the IP level timing constraint to SOC level, maintain all SOC level clocks definition and exceptions.
• Responsible for full timing constraints delivery to Physical Design, timing constraints quality, check timing result, and update timing result.
• Responsible for working with Physical design and IP teams to close timing by fix timing constraint issues
• Responsible for SOC level timing constraints signoff and work closely with IP for timing constraints review and signoff.
• Post silicon support to ensure successful bring up and enhance yield learning

PREFERRED EXPERIENCE:

• > 8 years working experience on SOC Implementation/Tapeout
• Have strong knowledge with digital signoff timing Methodology, constraint check rule for constraints quality verification.
• Familiar with primetime (PT) and galaxy constraint analyzer (GCA).
• Familiar with timing target definition methodology
• Familiar with SOC architecture and design knowledge, such as Serdes, AXI buses, source synchronous and test design.
• Strong commitment to schedule and quality of the timing constraint delivery in project’s each milestone.
• Have Experience on complex SOC full chip timing constraints delivery and timing quality check
• Have good communication skills and be able to work both independently and in a team.
• Collaborate with IP /PD team on the timing closure
• Good teamwork and leadership skills
• Good script development skills with experience with Perl/Shell scripting, and Verilog RTL design 

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering 

#LI-RD1

At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

SMTS SILICON DESIGN ENGINEER

THE ROLE: 

As a member of the Semi Custom Group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success.

THE PERSON:

A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills.

KEY RESPONSIBLITIES:

• Work closely with SOC Architecture team for SOC clocks statistical timing target goals.
• Responsible for merging the IP level timing constraint to SOC level, maintain all SOC level clocks definition and exceptions.
• Responsible for full timing constraints delivery to Physical Design, timing constraints quality, check timing result, and update timing result.
• Responsible for working with Physical design and IP teams to close timing by fix timing constraint issues
• Responsible for SOC level timing constraints signoff and work closely with IP for timing constraints review and signoff.
• Post silicon support to ensure successful bring up and enhance yield learning

PREFERRED EXPERIENCE:

• > 8 years working experience on SOC Implementation/Tapeout
• Have strong knowledge with digital signoff timing Methodology, constraint check rule for constraints quality verification.
• Familiar with primetime (PT) and galaxy constraint analyzer (GCA).
• Familiar with timing target definition methodology
• Familiar with SOC architecture and design knowledge, such as Serdes, AXI buses, source synchronous and test design.
• Strong commitment to schedule and quality of the timing constraint delivery in project’s each milestone.
• Have Experience on complex SOC full chip timing constraints delivery and timing quality check
• Have good communication skills and be able to work both independently and in a team.
• Collaborate with IP /PD team on the timing closure
• Good teamwork and leadership skills
• Good script development skills with experience with Perl/Shell scripting, and Verilog RTL design 

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering 

#LI-RD1