SMTS Silicon Design Engineer ( DFT Design Lead )

Feb 09, 2024
Bengaluru, India
... Not specified
... Intermediate
Full time
... Office work


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We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

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SMTS SILICON DESIGN ENGINEER - DFT (AECG ASIC)

THE ROLE: 

AECG SSD ASIC is a centralized ASIC design group within AMD’s Adaptive and Embedded Computing Organization. The group consists of design teams located in several AMD locations in North America and Asia. It is primarily responsible for architecture, design, and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features for cutting edge AMD products.

 

THE PERSON: 

As a DFx Silicon Design Engineer, you will be working with a team of design engineers from various global design locations on design-for-test (DFT) design and implementation, tool and methodology development, project execution and continuous improvement initiatives, this role provides an excellent growth opportunity for robust individuals looking to make a difference. This is an exciting time to join the AMD team! 

 

KEY RESPONSIBILITIES: 

  • Develop RTL for ASIC design-for-test (DFT) features as per architectural or design flow automation specifications.
  • Perform RTL design integration, insertion, synthesis, equivalency checking, timing analysis and closure including defining constraints.
  • Maintain tests for functional verification and performance verification at the SOC level.
  • Work with multi-functional teams and handling schedules
  • The successful candidate may also be responsible of:
    • Debugging and verifying block-/chip-level DFT/DFX features
    • Porting or creating the DFT/DFX verification environment.
    • Block/chip test plan creation and development
    • Stimulus writing and debug, and regression clean-up.
    • Generating high quality manufacturing test patterns for stuck-at, transition fault models and using on-chip test compression techniques
    • Simulating and verifying the ATPG and LBIST patterns
    • Working with the product engineering teams on the delivery of manufacturing test patterns.

PREFERRED EXPERIENCE: 

  • 8-12 years of DFT or related domains experience, leading DFT efforts for large processor and/or SOC designs is a plus.
  • Knowledge of DFT techniques such as JTAG/IEEE standards, Scan and ATPG, memory BIST/repair or Logic BIST
  • Good working knowledge of UNIX/Linux and scripting languages (e.g. TCL, c-shell, Perl)
  • Familiar with Verilog design language, Verilog simulator and waveform debugging tools
  • Knowledge of EDA tools/methodology, such as synthesis, equivalency checking, static timing analysis is a plus.
  • Strong problem-solving skills.
  • Team player with strong communication skills.

 

ACADEMIC CREDENTIALS: 

  • Bachelor’s or Master’s degree in electrical/Electronic Engineering 

 

LOCATION:

Bangalore, India

 

 

#LI-SR4




Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

SMTS SILICON DESIGN ENGINEER - DFT (AECG ASIC)

THE ROLE: 

AECG SSD ASIC is a centralized ASIC design group within AMD’s Adaptive and Embedded Computing Organization. The group consists of design teams located in several AMD locations in North America and Asia. It is primarily responsible for architecture, design, and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features for cutting edge AMD products.

 

THE PERSON: 

As a DFx Silicon Design Engineer, you will be working with a team of design engineers from various global design locations on design-for-test (DFT) design and implementation, tool and methodology development, project execution and continuous improvement initiatives, this role provides an excellent growth opportunity for robust individuals looking to make a difference. This is an exciting time to join the AMD team! 

 

KEY RESPONSIBILITIES: 

  • Develop RTL for ASIC design-for-test (DFT) features as per architectural or design flow automation specifications.
  • Perform RTL design integration, insertion, synthesis, equivalency checking, timing analysis and closure including defining constraints.
  • Maintain tests for functional verification and performance verification at the SOC level.
  • Work with multi-functional teams and handling schedules
  • The successful candidate may also be responsible of:
    • Debugging and verifying block-/chip-level DFT/DFX features
    • Porting or creating the DFT/DFX verification environment.
    • Block/chip test plan creation and development
    • Stimulus writing and debug, and regression clean-up.
    • Generating high quality manufacturing test patterns for stuck-at, transition fault models and using on-chip test compression techniques
    • Simulating and verifying the ATPG and LBIST patterns
    • Working with the product engineering teams on the delivery of manufacturing test patterns.

PREFERRED EXPERIENCE: 

  • 8-12 years of DFT or related domains experience, leading DFT efforts for large processor and/or SOC designs is a plus.
  • Knowledge of DFT techniques such as JTAG/IEEE standards, Scan and ATPG, memory BIST/repair or Logic BIST
  • Good working knowledge of UNIX/Linux and scripting languages (e.g. TCL, c-shell, Perl)
  • Familiar with Verilog design language, Verilog simulator and waveform debugging tools
  • Knowledge of EDA tools/methodology, such as synthesis, equivalency checking, static timing analysis is a plus.
  • Strong problem-solving skills.
  • Team player with strong communication skills.

 

ACADEMIC CREDENTIALS: 

  • Bachelor’s or Master’s degree in electrical/Electronic Engineering 

 

LOCATION:

Bangalore, India

 

 

#LI-SR4

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