WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

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SMTS SILICON DESIGN ENGINEER

THE ROLE: 

As a member of the AECG Wired IP Solutions Group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success.

THE PERSON:

A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills.

KEY RESPONSIBLITIES:

• Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified 
• Define verification infrastructure for IP being designed
• Help in dissemination of verification responsibilities to team
• Mentor verification engineers, guiding them in resolving issues
• Tracking of project to ensure that schedules are being adhered to

PREFERRED EXPERIENCE:

• B.E/M.E/M.Tech or B.S/M.S in EE/ECE with at least 12+ years of relevant experience in IP verification
• Strong understanding and experience in verification of Ethernet protocols and IEEE 802.3 standards both MAC and PCS/PMA
• Knowledge on Ethernet protocols and standards like 1588, Pause, FEC, RSFEC, AN/LT, TSN and speeds from 1GE up to 100GE and beyond
• Knowledge on high speed serial transceiver GT and interface
• Strong domain knowledge of interfaces which include AXI streaming and high Speed serial connectivity etc
• Proven end to end verification of complex IP using System Verilog and latest methodologies like UVM
• Proficient knowledge of System Verilog, HVL based methodology and hands on scripting experience for automations
• Experience in verification including constrained-random, coverage driven verification environments
• Strong debugging, testing and verification skills
• Should have handled verification of complex RTL designs by developing test cases and test benches including coverage analysis and UNH verification
• Having System level knowledge / Verifying IP at system level will be a definite plus
• Knowledge of FPGA architecture and working experience with Xilinx Implementation tools is an added advantage
• Self-driven, motivated, result oriented individual with superior academic achievements
• Excellent interpersonal, written, group communication and problem solving  skills and very good team player
• Good organizational and execution skills with ability to multi-task and prioritize and able to work on deadlines with high quality deliverables
• Good in SystemVerilog and modern verification libraries like UVM 
• Must have working experience in Ethernet  
• Having worked on switches/switching protocols is an added advantage
• Proficient in IP level ASIC verification 
• Proficient in debugging firmware and RTL code using simulation tools  
• Proficient in developing and using UVM testbenches , processes and flows and working in Linux and Windows environments 
• Automating workflows in a distributed compute environment.   
• Good working knowledge of SystemC and TLM with some related experience.   
• Scripting language experience: Perl, Ruby, Makefile, shell preferred.   
• Exposure to leadership or mentorship is an asset 

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering 
  
  
  #LI-RP1

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

SMTS SILICON DESIGN ENGINEER

THE ROLE: 

As a member of the AECG Wired IP Solutions Group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success.

THE PERSON:

A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills.

KEY RESPONSIBLITIES:

• Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified 
• Define verification infrastructure for IP being designed
• Help in dissemination of verification responsibilities to team
• Mentor verification engineers, guiding them in resolving issues
• Tracking of project to ensure that schedules are being adhered to

PREFERRED EXPERIENCE:

• B.E/M.E/M.Tech or B.S/M.S in EE/ECE with at least 12+ years of relevant experience in IP verification
• Strong understanding and experience in verification of Ethernet protocols and IEEE 802.3 standards both MAC and PCS/PMA
• Knowledge on Ethernet protocols and standards like 1588, Pause, FEC, RSFEC, AN/LT, TSN and speeds from 1GE up to 100GE and beyond
• Knowledge on high speed serial transceiver GT and interface
• Strong domain knowledge of interfaces which include AXI streaming and high Speed serial connectivity etc
• Proven end to end verification of complex IP using System Verilog and latest methodologies like UVM
• Proficient knowledge of System Verilog, HVL based methodology and hands on scripting experience for automations
• Experience in verification including constrained-random, coverage driven verification environments
• Strong debugging, testing and verification skills
• Should have handled verification of complex RTL designs by developing test cases and test benches including coverage analysis and UNH verification
• Having System level knowledge / Verifying IP at system level will be a definite plus
• Knowledge of FPGA architecture and working experience with Xilinx Implementation tools is an added advantage
• Self-driven, motivated, result oriented individual with superior academic achievements
• Excellent interpersonal, written, group communication and problem solving  skills and very good team player
• Good organizational and execution skills with ability to multi-task and prioritize and able to work on deadlines with high quality deliverables
• Good in SystemVerilog and modern verification libraries like UVM 
• Must have working experience in Ethernet  
• Having worked on switches/switching protocols is an added advantage
• Proficient in IP level ASIC verification 
• Proficient in debugging firmware and RTL code using simulation tools  
• Proficient in developing and using UVM testbenches , processes and flows and working in Linux and Windows environments 
• Automating workflows in a distributed compute environment.   
• Good working knowledge of SystemC and TLM with some related experience.   
• Scripting language experience: Perl, Ruby, Makefile, shell preferred.   
• Exposure to leadership or mentorship is an asset 

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering 
  
  
  #LI-RP1