WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. This is who we are at our best. One Company. One Team. 

AMD together we advance_

The Role:

As a member of the Radeon Technologies Group you will help bring to life cutting edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success.

Key Responsibilities:

• Develop RTL and integrate internal/external RTL logic into SoC (System-On-Chip)
• Write and review verification test-plans
• Develop verification infrastructure, test-bench components and test-cases
• Drive performance verification on all DFT structures
• Generate and verify DFT structural patterns and functional patterns
• Verification of Scan Initilization Sequence
• Scan insertion and ATPG pattern generation & verification of Scan Initilization Sequence
• ATPG patterns verification with gate level simulation
• Test coverage and test cost reduction analysis
• Post silicon support to ensure successful bringup and enhance yield learning

Preferred Experience:

• Master with at least 5 years or Bachelor with at least 8 years working experience in ASIC DFT area.
• Understanding of Design For Test methodologies and DFT verification experience (eg. IEEE1500, JTAG 1149.x, scan, memory BIST, ? etc)
• Very strong background in Verilog, System Verilog, C/C++/OO coding techniques
• Experience working with industry standard synthesis tools, flows and timing closure(Formality, CDC&Linting tools, Design Compiler/FX etc)
• Experience working with Cadence NCSIM, Synopsys VCS or equivalent
• Experience working with UVM, OVM or equivalent
• Experience with Mentor testkompress and/or Synopsys Tetramax/DFTMAX
• Excellent oral, written and interpersonal communication skills
• Strong analytical skills and attention to detail
• Must be a self-starter and able to independently drive tasks to completion.
• Demonstrates the ability to debug issues and quickly identify viable solutions
• Team player with proven leadership skills

Location:

Markham, CA, Austin, TX or Orlando, FL

#LI-PH1

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

The Role:

As a member of the Radeon Technologies Group you will help bring to life cutting edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success.

Key Responsibilities:

• Develop RTL and integrate internal/external RTL logic into SoC (System-On-Chip)
• Write and review verification test-plans
• Develop verification infrastructure, test-bench components and test-cases
• Drive performance verification on all DFT structures
• Generate and verify DFT structural patterns and functional patterns
• Verification of Scan Initilization Sequence
• Scan insertion and ATPG pattern generation & verification of Scan Initilization Sequence
• ATPG patterns verification with gate level simulation
• Test coverage and test cost reduction analysis
• Post silicon support to ensure successful bringup and enhance yield learning

Preferred Experience:

• Master with at least 5 years or Bachelor with at least 8 years working experience in ASIC DFT area.
• Understanding of Design For Test methodologies and DFT verification experience (eg. IEEE1500, JTAG 1149.x, scan, memory BIST, ? etc)
• Very strong background in Verilog, System Verilog, C/C++/OO coding techniques
• Experience working with industry standard synthesis tools, flows and timing closure(Formality, CDC&Linting tools, Design Compiler/FX etc)
• Experience working with Cadence NCSIM, Synopsys VCS or equivalent
• Experience working with UVM, OVM or equivalent
• Experience with Mentor testkompress and/or Synopsys Tetramax/DFTMAX
• Excellent oral, written and interpersonal communication skills
• Strong analytical skills and attention to detail
• Must be a self-starter and able to independently drive tasks to completion.
• Demonstrates the ability to debug issues and quickly identify viable solutions
• Team player with proven leadership skills

Location:

Markham, CA, Austin, TX or Orlando, FL

#LI-PH1