Markham, Canada
Not specified
Intermediate
Office work
WHAT YOU DO AT AMD CHANGES EVERYTHING
We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.
AMD together we advance_
SMTS SILICON DESIGN ENGINEER
PD clock engineer
THE ROLE:
The scoping of PD clock engineer includes implementing global clock in layout, running SPICE simulation, clock related STA, sending feedback to integration team. AMD design is big and complex with advanced process and technology. PD clock owner needs to have rich experience in PnR EDA tools/PrimeTime/SPICE-simulator, and will be able to deliver high quality clock implementation on schedule. The owner needs co-work with full-chip-floorplan/timing/integration/IP teams, meet clock layout/electrical constraints and accommodate IP/timing requirements.
THE PERSON:
- > 5 years working experience on Physical Design
- Knowledgeable in Physical Design flow, especially clock related
- Familiar with PnR EDA tools, SPICE simulation as a plus
- Good teamwork and script skills
- Good learning skills to ramp-up quickly
KEY RESPONSIBILITIES:
- Implement chip level clocks in layout on schedule
- Send feedback to front-end
- Co-work with PnR/timing team to adjustment clock design
- Run SPICE simulation to analyze and fix violations
- Do RDL layer routing and clean up DRC
PREFERRED EXPERIENCE:
- Chip level clock implementation with ICC2/FunsionCompiler/Innovus
- PnR and Static Timing Analysis(PrimeTime)
- SPICE simulators like Hspice
- Good at scripts, like Python/perl/Tcl/Shell
#LI-RD1
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
SMTS SILICON DESIGN ENGINEER
PD clock engineer
THE ROLE:
The scoping of PD clock engineer includes implementing global clock in layout, running SPICE simulation, clock related STA, sending feedback to integration team. AMD design is big and complex with advanced process and technology. PD clock owner needs to have rich experience in PnR EDA tools/PrimeTime/SPICE-simulator, and will be able to deliver high quality clock implementation on schedule. The owner needs co-work with full-chip-floorplan/timing/integration/IP teams, meet clock layout/electrical constraints and accommodate IP/timing requirements.
THE PERSON:
- > 5 years working experience on Physical Design
- Knowledgeable in Physical Design flow, especially clock related
- Familiar with PnR EDA tools, SPICE simulation as a plus
- Good teamwork and script skills
- Good learning skills to ramp-up quickly
KEY RESPONSIBILITIES:
- Implement chip level clocks in layout on schedule
- Send feedback to front-end
- Co-work with PnR/timing team to adjustment clock design
- Run SPICE simulation to analyze and fix violations
- Do RDL layer routing and clean up DRC
PREFERRED EXPERIENCE:
- Chip level clock implementation with ICC2/FunsionCompiler/Innovus
- PnR and Static Timing Analysis(PrimeTime)
- SPICE simulators like Hspice
- Good at scripts, like Python/perl/Tcl/Shell
#LI-RD1
