SMTS Silicon Design Engineer

Oct 04, 2023
Markham, Canada
... Not specified
... Intermediate
Full time
... Office work


WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_




SMTS SILICON DESIGN ENGINEER

 

THE ROLE: 

 

Implementing and supporting Synthesis and Place&Route Flows for a world-class Physical Design team working on IC’s targeted for Gaming Consoles,  Low-Power AR devices and Hand-Held Gaming ,  Ultra-thin Laptops, etc..

You will work with the support of an excellent AMD CAD organization,  and on the most advanced Tools, Flows, and Tech nodes.

KEY RESPONSIBLITIES INCLUDE (BUT NOT LIMITED TO):

 

Setting up and supporting flows for:

    • Block level synthesis
    • Design-for-Power using Industry Standard Tools and Methods
    • Place and Route, Clock Tree Synthesis
    • ECO flow for timing and functional fixes
    • Physical Design verification and analysis flow
    • Optimize Physical Design Techniques to optimize for Power, Performance, and/or Area
    • Enable Physical Design flows in new Technology nodes
    • Updated tool versions and settings to support new nodes
    • Support Physical Design Teams with critical Implementation challenges


QUALIFICATIONS:

Bachelor's Degree in Electrical/ Electronics/Computer Engineering or a directly related discipline with 8+ years of physical design experience. OR a Master’s degree in same fields with 4+ years of physical design experience. OR a PhD degree in same fields with 2+ years of physical design experience:

 

Your expertise must be in one, or more, of the following areas:

  • ASIC physical design implementation
  • Block level implementation (Place and Route), which includes Floorplanning, Timing Closure and Physical Verification
  • Physical Design verification signoff techniques such as Formal equivalence, IR&EM, Timing Closure (STA), Physical verification, VSI, Formal Equivalence Check or LEC, etc.
  • Use of Industry Standard tools for CAD flow development and methodology practicing Auto Place and Route and Strategies for Static Timing Analysis
  • Power, Performance and Area (PPA) optimization techniques
  • Proficiency in Debugging CAD Flow issues using Industry standard Silicon Design tools: from Synopsys, Cadence, Mentor Graphics ( Fusion Complier, Synopsys ICC2, Innovus, Primetime, Spyglass, RedHawk, VSI, Calibre etc.)

Preferred qualifications

  • Unix, Linux, Python, Perl, TCL programming

#LI-RD1




Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

SMTS SILICON DESIGN ENGINEER

 

THE ROLE: 

 

Implementing and supporting Synthesis and Place&Route Flows for a world-class Physical Design team working on IC’s targeted for Gaming Consoles,  Low-Power AR devices and Hand-Held Gaming ,  Ultra-thin Laptops, etc..

You will work with the support of an excellent AMD CAD organization,  and on the most advanced Tools, Flows, and Tech nodes.

KEY RESPONSIBLITIES INCLUDE (BUT NOT LIMITED TO):

 

Setting up and supporting flows for:

    • Block level synthesis
    • Design-for-Power using Industry Standard Tools and Methods
    • Place and Route, Clock Tree Synthesis
    • ECO flow for timing and functional fixes
    • Physical Design verification and analysis flow
    • Optimize Physical Design Techniques to optimize for Power, Performance, and/or Area
    • Enable Physical Design flows in new Technology nodes
    • Updated tool versions and settings to support new nodes
    • Support Physical Design Teams with critical Implementation challenges


QUALIFICATIONS:

Bachelor's Degree in Electrical/ Electronics/Computer Engineering or a directly related discipline with 8+ years of physical design experience. OR a Master’s degree in same fields with 4+ years of physical design experience. OR a PhD degree in same fields with 2+ years of physical design experience:

 

Your expertise must be in one, or more, of the following areas:

  • ASIC physical design implementation
  • Block level implementation (Place and Route), which includes Floorplanning, Timing Closure and Physical Verification
  • Physical Design verification signoff techniques such as Formal equivalence, IR&EM, Timing Closure (STA), Physical verification, VSI, Formal Equivalence Check or LEC, etc.
  • Use of Industry Standard tools for CAD flow development and methodology practicing Auto Place and Route and Strategies for Static Timing Analysis
  • Power, Performance and Area (PPA) optimization techniques
  • Proficiency in Debugging CAD Flow issues using Industry standard Silicon Design tools: from Synopsys, Cadence, Mentor Graphics ( Fusion Complier, Synopsys ICC2, Innovus, Primetime, Spyglass, RedHawk, VSI, Calibre etc.)

Preferred qualifications

  • Unix, Linux, Python, Perl, TCL programming

#LI-RD1

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