SMTS Silicon Design Engineer

Feb 16, 2024
Markham, Canada
... Not specified
... Intermediate
Full time
... Office work

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_

Multimedia IP Design Engineer(s)

 

THE ROLE:

The Multimedia IP(MMIP) team is looking for multiple design positions to be filled.   As a key contributor, you would be leading teams to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The MMIP team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.

 

THE PERSON: 

You have a passion for modern, complex processor architecture, digital low power design, logical/physical implementation and verification in general.  You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites & time zones. You have strong analytical and problem-solving skills and are willing to learn and are ready to take on new challenges.

 

KEY RESPONSIBILITIES:

 

Low power Design Engineer:

  • Collaborate with global Video IP development teams, firmware engineers on Video IP Power methodology and SoC integration aligned to SoC milestones.
  • Work with SoC teams related to the IP power features, implement low power features and publish power metrics.
  • Develop low power RTL techniques and implement in VCN IP power environment.
  • Develop System Verilog, C-model, and C++ bus functional models for specific features.
  • Develop or adapt, and verify IP PG/NLP tests, PA CDC, UPF Params, XOVER metrics.
  • Work with SoC Power team to debug power numbers and test failures and debug at IP and chip level.

 

Design Integration Engineer:

  • Drive IP design quality with broader IP team to meet Power/Performance/Area goals through synthesis, CDC, LINT, timing closure etc
  • Drive bottoms up IP/SOC design to ensure successful consumption of the IP within the context of an SOC
  • Collaborate directly with both IP and SOC Architecture and Design Leads. 
  • Provide guidance and/or act as a liaison between IP and SOC design teams for design, synthesis and physical layout issues 
  • Provide hands on leadership of a small team of Engineers/Engineers in Training to meet IP goals
  • Signoff IP quality for high volume AMD SOC programs
  • Effectively communicate with various multi-discipline teams located across the globe
  • Represent Display IP interests in various technical steering bodies
  • Attend and present into technical status meetings

 

PREFERRED EXPERIENCE :

  • Proficient in Digital Logic design, IP Low Power methodology and SoC integration
  • 8+ years of hands-on RTL design experience in ASIC product development.
  • Strong knowledge on low power techniques, industry standard power flows.
  • Strong background working with industry leading Synthesis tools, flows and back-end timing closure(e.g. Formality, CDC, LINT, Design Compiler/FX etc).
  • Proficient in System Verilog, UVM test benches, UPF flow and scripting languages (csh, perl, Python, etc.).
  • Proficient in simulation & debugging

 

ACADEMIC CREDENTIALS:

  • BS degree in Electrical or Computer Engineering
  • MS degree preferred

 #LI-PU1

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Multimedia IP Design Engineer(s)

 

THE ROLE:

The Multimedia IP(MMIP) team is looking for multiple design positions to be filled.   As a key contributor, you would be leading teams to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The MMIP team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.

 

THE PERSON: 

You have a passion for modern, complex processor architecture, digital low power design, logical/physical implementation and verification in general.  You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites & time zones. You have strong analytical and problem-solving skills and are willing to learn and are ready to take on new challenges.

 

KEY RESPONSIBILITIES:

 

Low power Design Engineer:

  • Collaborate with global Video IP development teams, firmware engineers on Video IP Power methodology and SoC integration aligned to SoC milestones.
  • Work with SoC teams related to the IP power features, implement low power features and publish power metrics.
  • Develop low power RTL techniques and implement in VCN IP power environment.
  • Develop System Verilog, C-model, and C++ bus functional models for specific features.
  • Develop or adapt, and verify IP PG/NLP tests, PA CDC, UPF Params, XOVER metrics.
  • Work with SoC Power team to debug power numbers and test failures and debug at IP and chip level.

 

Design Integration Engineer:

  • Drive IP design quality with broader IP team to meet Power/Performance/Area goals through synthesis, CDC, LINT, timing closure etc
  • Drive bottoms up IP/SOC design to ensure successful consumption of the IP within the context of an SOC
  • Collaborate directly with both IP and SOC Architecture and Design Leads. 
  • Provide guidance and/or act as a liaison between IP and SOC design teams for design, synthesis and physical layout issues 
  • Provide hands on leadership of a small team of Engineers/Engineers in Training to meet IP goals
  • Signoff IP quality for high volume AMD SOC programs
  • Effectively communicate with various multi-discipline teams located across the globe
  • Represent Display IP interests in various technical steering bodies
  • Attend and present into technical status meetings

 

PREFERRED EXPERIENCE :

  • Proficient in Digital Logic design, IP Low Power methodology and SoC integration
  • 8+ years of hands-on RTL design experience in ASIC product development.
  • Strong knowledge on low power techniques, industry standard power flows.
  • Strong background working with industry leading Synthesis tools, flows and back-end timing closure(e.g. Formality, CDC, LINT, Design Compiler/FX etc).
  • Proficient in System Verilog, UVM test benches, UPF flow and scripting languages (csh, perl, Python, etc.).
  • Proficient in simulation & debugging

 

ACADEMIC CREDENTIALS:

  • BS degree in Electrical or Computer Engineering
  • MS degree preferred

 #LI-PU1

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