SMTS Silicon Design Engineer

Mar 13, 2024
Not specified,
... Not specified
... Intermediate
Full time
... Office work


WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_




THE ROLE:

AMD NBIO (North Bridge IO) team delivers industry leading high-performance interconnects IP subsystems for all AMD products including Gaming APU and GPU, Client Desktop and Laptop APU, Server CPU and GPU etc. IP subsystems delivered by global NBIO organization includes PCIe, IOHUB (for high speed IO device routing and IO virtualization), CIT (for high speed interconnect among chiplets), DACC (for IO acceleration) and future opportunities. Global NBIO organization operates seamless from China, North America and Europe.

 

NBIO multi-subsystem interoperability, performance and emulation (MPME) team focus on interoperability verification, performance & power verification across subsystems, delivers performance architect models and emulation solutions for NBIO subsystems.

 

THE PERSON:

The successful candidate for this role will be an integral part of MPME team and focus on Multi-Subsystem Verification.  We are seeking a forward thinker to improve development process and drive innovation.

 

KEY RESPONSIBILITIES:

  • Be responsible for leading MPME project execution and tracking team’s status
  • Be involved technically in the porting/creation of the DV environment for the new design, test plan creation, review and implementation, coverage analysis, and regression cleanup
  • Forward thinker to improve development process and drive innovation
  • Collaborate with global engineering team on implementation of multiple programs
  • Provide technical guidance to junior engineers

PREFERRED EXPERIENCE:

  • Solid knowledge on SystemVerilog, UVM, C/C++, Verilog
  • Solid background with hardware verification methodologies such as coverage-based verification methodology with the use of hardware assertions (PSL or SVA)
  • Solid knowledge on scripting language like Perl, Python, Ruby
  • Hands on experiences on NLP and be familiar with UPF is a big plus
  • Knowledge on PCIE is a big plus
  • Fluent verbal English for technical discussion with global team
  • Hands on experience on leading project execution

ACADEMIC CREDENTIALS:

  • Candidate is preferred to be MSEE with 8 years, or BSEE with 10-years experience in digital ASIC/SOC design verification.

LOCATION:

Penang, Malaysia

 

#LI-FY

#LI-Hybrid

 




Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

THE ROLE:

AMD NBIO (North Bridge IO) team delivers industry leading high-performance interconnects IP subsystems for all AMD products including Gaming APU and GPU, Client Desktop and Laptop APU, Server CPU and GPU etc. IP subsystems delivered by global NBIO organization includes PCIe, IOHUB (for high speed IO device routing and IO virtualization), CIT (for high speed interconnect among chiplets), DACC (for IO acceleration) and future opportunities. Global NBIO organization operates seamless from China, North America and Europe.

 

NBIO multi-subsystem interoperability, performance and emulation (MPME) team focus on interoperability verification, performance & power verification across subsystems, delivers performance architect models and emulation solutions for NBIO subsystems.

 

THE PERSON:

The successful candidate for this role will be an integral part of MPME team and focus on Multi-Subsystem Verification.  We are seeking a forward thinker to improve development process and drive innovation.

 

KEY RESPONSIBILITIES:

  • Be responsible for leading MPME project execution and tracking team’s status
  • Be involved technically in the porting/creation of the DV environment for the new design, test plan creation, review and implementation, coverage analysis, and regression cleanup
  • Forward thinker to improve development process and drive innovation
  • Collaborate with global engineering team on implementation of multiple programs
  • Provide technical guidance to junior engineers

PREFERRED EXPERIENCE:

  • Solid knowledge on SystemVerilog, UVM, C/C++, Verilog
  • Solid background with hardware verification methodologies such as coverage-based verification methodology with the use of hardware assertions (PSL or SVA)
  • Solid knowledge on scripting language like Perl, Python, Ruby
  • Hands on experiences on NLP and be familiar with UPF is a big plus
  • Knowledge on PCIE is a big plus
  • Fluent verbal English for technical discussion with global team
  • Hands on experience on leading project execution

ACADEMIC CREDENTIALS:

  • Candidate is preferred to be MSEE with 8 years, or BSEE with 10-years experience in digital ASIC/SOC design verification.

LOCATION:

Penang, Malaysia

 

#LI-FY

#LI-Hybrid

 

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