SMTS Silicon Design Engineer

Jan 31, 2024
Shanghai, China
... Not specified
... Intermediate
Full time
... Office work
Overview

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_


Responsibilities

SMTS SILICON DESIGN ENGINEER

THE ROLE:

10G/25G/100G Ethernet Controller IP Integration

 

THE PERSON:

Good communicate skill, co-work spirit, strong self-learning and adaptability are preferring.

 

KEY RESPONSIBILITIES:

  • 10G/25G/100G Ethernet Controller IP Integration
  • SR-IOV Development
  • Work as IP design lead with potential grow to IP owner.
  • Work with SOC/IP architect, system engineering team, and SW/FW teams to create IP features and define micro-architecture for client/server/embedded SOC products.
  • Work on RTL Design implementation, LINT/CDC, Synthesis and Timing closure.
  • Work closely with SOC team to ensure IP delivery meets with requirements.
  • Work closely with SW, FW and system engineering teams on post-silicon bring-up/debug till production.
  • Participate in IP/Company’s methodology improvement, and new technology/architecture definition.

 

PREFERRED EXPERIENCE:

  • Excellent knowledge of Verilog, System Verilog and a scripting language; experience with Perl, Tcl and Ruby is a plus.
  • Solid x86 system architecture knowledge is a must, familiar with the traditional PC I/O interfaces especially in the area of Ethernet or PCIe.
  • One or more of the follow I/O IP design experiences is very helpful, Ethernet/PCIe/USB/SATA/NVME, etc.
  • The capability of understanding and analyzing I/O performance/power consumption based on IP design is necessary.
  • Working knowledge/experience with I/O SW driver and FW is a plus.
  • Security/cryptography knowledge is a plus
  • Strong analytical/problem solving skills and pronounced attention to details.
  • Self-motivated team player, and able to independently drive tasks to completion.
  • Strong and clear communication skill, fluent in English are required.

 

ACADEMIC CREDENTIALS:

  • MSEE within 4-8 years, or BSEE within 6-10 years’ experience complex IP design with strong IP design knowledge/experience.

 

LOCATION:

Shanghai

 

 

#LI-JG2 #HYBRID


Qualifications

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

SMTS SILICON DESIGN ENGINEER

THE ROLE:

10G/25G/100G Ethernet Controller IP Integration

 

THE PERSON:

Good communicate skill, co-work spirit, strong self-learning and adaptability are preferring.

 

KEY RESPONSIBILITIES:

  • 10G/25G/100G Ethernet Controller IP Integration
  • SR-IOV Development
  • Work as IP design lead with potential grow to IP owner.
  • Work with SOC/IP architect, system engineering team, and SW/FW teams to create IP features and define micro-architecture for client/server/embedded SOC products.
  • Work on RTL Design implementation, LINT/CDC, Synthesis and Timing closure.
  • Work closely with SOC team to ensure IP delivery meets with requirements.
  • Work closely with SW, FW and system engineering teams on post-silicon bring-up/debug till production.
  • Participate in IP/Company’s methodology improvement, and new technology/architecture definition.

 

PREFERRED EXPERIENCE:

  • Excellent knowledge of Verilog, System Verilog and a scripting language; experience with Perl, Tcl and Ruby is a plus.
  • Solid x86 system architecture knowledge is a must, familiar with the traditional PC I/O interfaces especially in the area of Ethernet or PCIe.
  • One or more of the follow I/O IP design experiences is very helpful, Ethernet/PCIe/USB/SATA/NVME, etc.
  • The capability of understanding and analyzing I/O performance/power consumption based on IP design is necessary.
  • Working knowledge/experience with I/O SW driver and FW is a plus.
  • Security/cryptography knowledge is a plus
  • Strong analytical/problem solving skills and pronounced attention to details.
  • Self-motivated team player, and able to independently drive tasks to completion.
  • Strong and clear communication skill, fluent in English are required.

 

ACADEMIC CREDENTIALS:

  • MSEE within 4-8 years, or BSEE within 6-10 years’ experience complex IP design with strong IP design knowledge/experience.

 

LOCATION:

Shanghai

 

 

#LI-JG2 #HYBRID

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