SMTS Silicon Design Engineer

Feb 25, 2024
Shanghai, China
... Not specified
... Intermediate
Full time
... Office work


WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_




SMTS SILICON DESIGN ENGINEER

THE ROLE:

 

Control Fabric (CF) IP is the backbone of AMD SOCs. We design and deliver cutting-edge technologies of network-on-chip (NoC), chiplet interconnect, advanced power & thermal management, clocking, etc. The SRDC CF IP team is the central part of global CF team.

 

THE PERSON:

 

If you’re: self-motivated, passionate to push the boundary and explore new territory, believer of sharing and mutual influence, you’re exactly who we look for.

 

  • Develop comprehensive block level verification testplan for DUT
  • Develop testbench and testcases with SystemVerilog/UVM verification methodology
  • Develop verification IP which can be reused at different levels of verification, including block, sub-system, SoC, etc
  • Support sub-system and SOC level verification

 

PREFERRED EXPERIENCE:

  • Excellent knowledge of design verification methodology, such as UVM, System Verilog, Formal
  • Solid experiences with simulation model creation and the testbench build
  • UPF/CPF based power-aware simulation experience is a plus
  • C/C++ software development experiences is a plus
  • Good communication skill and fluent English

 

ACADEMIC CREDENTIALS:

  • Master or Bachelor degree in EE/CS is preferred
  • At least 10 years of related work experience

 

LOCATION:

Shanghai

 

#LI-VC1

 




Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

SMTS SILICON DESIGN ENGINEER

THE ROLE:

 

Control Fabric (CF) IP is the backbone of AMD SOCs. We design and deliver cutting-edge technologies of network-on-chip (NoC), chiplet interconnect, advanced power & thermal management, clocking, etc. The SRDC CF IP team is the central part of global CF team.

 

THE PERSON:

 

If you’re: self-motivated, passionate to push the boundary and explore new territory, believer of sharing and mutual influence, you’re exactly who we look for.

 

  • Develop comprehensive block level verification testplan for DUT
  • Develop testbench and testcases with SystemVerilog/UVM verification methodology
  • Develop verification IP which can be reused at different levels of verification, including block, sub-system, SoC, etc
  • Support sub-system and SOC level verification

 

PREFERRED EXPERIENCE:

  • Excellent knowledge of design verification methodology, such as UVM, System Verilog, Formal
  • Solid experiences with simulation model creation and the testbench build
  • UPF/CPF based power-aware simulation experience is a plus
  • C/C++ software development experiences is a plus
  • Good communication skill and fluent English

 

ACADEMIC CREDENTIALS:

  • Master or Bachelor degree in EE/CS is preferred
  • At least 10 years of related work experience

 

LOCATION:

Shanghai

 

#LI-VC1

 

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