SMTS Silicon Design Engineer

Mar 13, 2024
Singapore, Singapore
... Not specified
... Intermediate
Full time
... Office work


WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_




THE ROLE: 

 

As a SMTS Silicon Design Engineer in Serdes Technology group, you will work on Post-Silicon - DDR /IO validation, characterization, and Memory IO feature enablement/optimization lead to join a talented and experienced high speed IO design team.The team has a hands-on attitude, opportunities to learn and grow and a culture of innovation and pushing the performance boundaries. The team has great mentors in the field of Physical Layer (PHY) architecture, mixed signal analog-digital IO/circuit designs with industry veteran architects and designers who know how to build and deliver leadership mixed signal IPs for AMD products.


THE PERSON:

 

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

KEY RESPONSIBLITIES:

  • The Senior Technical Member in the post silicon validation and characterization lead for state of the art mixed signal silicon IP designs such as LPDDR/DDR/MIPI C-PHY/MIPI D-PHY/UCIE.
  • Be the "point person" for engaging directly with memory controller, SOC, platform, and DDR vendors and customers. Helping to root cause issues, understand and address concerns and to devise solutions.
  • Coach and provide guidance to junior members within the team.
  • Represent the IP org in the business unit VnC workstreams and Program Ops reviews.
  • Collaborate with the IP team and co-Own writing test plans, executing test plan in post silicon environments, perform debugging and failure analysis alongside the Silicon and Board design engineers to identify and fix any hardware bugs before going into production. Develop plans and track progress to meet go-to-production timelines.
  • Work with the platform/SOC and BU teams to plan VnC logistics such as Setup DDR4/5 pre/post-silicon validation environment, boards, test equipment.
  • Collaborate with SIPI teams and Contribute towards SI/PI related debug & testing, IO tuning, compliance testing and PVT characterization.
  • Develop softIP, firmware, and software/script routines for DDR PHY/DRAM initialization / training routines, equalization & IO tuning, SI/PI related optimization, etc.
  • Validate and characterize the silicon on reference platform board system and execute data collection, Approved vendor list test, interoperability and compliance testing (DDR DIMM, MIPI Compliance).
  • Pull together regular project status presentations for next level management leadership review.  Convert large amounts of data into a clear story to communicate to peers and next level management. Identify risks, develop mitigation strategies & facilitate conflict resolution.

PREFERRED EXPERIENCE:

  • 10+ years post-silicon characterization and validation experience including DRAM initialization / Training, Input/Output (I/O), Signal Integrity (SI) tuning and Margin Optimization, DDR/MIPI/High Speed IO SerDes (PHY) design/validation, pre-/post-silicon verification. 
  • Extensive knowledge of the physical and protocol levels of latest industry standards of DDR4/5, LPDDR4/5, MIPI D-PHY/M-PHY.
  • Expertise in SI integrity measurements, equalization features validation and related tuning.
  • Experience in dealing directly with IP and DDR vendors/customers.
  • Customer-focused skills as a Hardware Application Engineer highly-desirable.
  • Experience in developing and testing DDR sub systems including working experience with DDR controller and PHY, JEDEC and DFI specifications
  • Microcontroller & Embedded Systems Programming Experience in C/C++
  • Understanding of ASIC/SOC boot flow and specifically DDR initialization process is highly desirable
  • Extensive experience with common lab equipment, including BERT, analyzers, oscilloscopes, PNA/VNA etc,.
  • Knowledge of High-speed analog and VLSI design, transmission-line theory.
  • Debug skills at both SoC and system level.
  • Strong programming/scripting skills (eg. Python, C/C++, Perl, TCL, Linux Sheel Script, etc.) for test methodology development and test automation
  • Excellent written and verbal interpersonal skills. Able to draft and manage technical documentations workflows such as Arch and uArch specs/user guides, with professional quality levels.

ACADEMIC CREDENTIALS:

  • Bachelors or Masters degree in computer engineering/Electrical Engineering

LOCATION:

Singapore

 

#LI-MM1

#LI-HYBRID




Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

THE ROLE: 

 

As a SMTS Silicon Design Engineer in Serdes Technology group, you will work on Post-Silicon - DDR /IO validation, characterization, and Memory IO feature enablement/optimization lead to join a talented and experienced high speed IO design team.The team has a hands-on attitude, opportunities to learn and grow and a culture of innovation and pushing the performance boundaries. The team has great mentors in the field of Physical Layer (PHY) architecture, mixed signal analog-digital IO/circuit designs with industry veteran architects and designers who know how to build and deliver leadership mixed signal IPs for AMD products.


THE PERSON:

 

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

KEY RESPONSIBLITIES:

  • The Senior Technical Member in the post silicon validation and characterization lead for state of the art mixed signal silicon IP designs such as LPDDR/DDR/MIPI C-PHY/MIPI D-PHY/UCIE.
  • Be the "point person" for engaging directly with memory controller, SOC, platform, and DDR vendors and customers. Helping to root cause issues, understand and address concerns and to devise solutions.
  • Coach and provide guidance to junior members within the team.
  • Represent the IP org in the business unit VnC workstreams and Program Ops reviews.
  • Collaborate with the IP team and co-Own writing test plans, executing test plan in post silicon environments, perform debugging and failure analysis alongside the Silicon and Board design engineers to identify and fix any hardware bugs before going into production. Develop plans and track progress to meet go-to-production timelines.
  • Work with the platform/SOC and BU teams to plan VnC logistics such as Setup DDR4/5 pre/post-silicon validation environment, boards, test equipment.
  • Collaborate with SIPI teams and Contribute towards SI/PI related debug & testing, IO tuning, compliance testing and PVT characterization.
  • Develop softIP, firmware, and software/script routines for DDR PHY/DRAM initialization / training routines, equalization & IO tuning, SI/PI related optimization, etc.
  • Validate and characterize the silicon on reference platform board system and execute data collection, Approved vendor list test, interoperability and compliance testing (DDR DIMM, MIPI Compliance).
  • Pull together regular project status presentations for next level management leadership review.  Convert large amounts of data into a clear story to communicate to peers and next level management. Identify risks, develop mitigation strategies & facilitate conflict resolution.

PREFERRED EXPERIENCE:

  • 10+ years post-silicon characterization and validation experience including DRAM initialization / Training, Input/Output (I/O), Signal Integrity (SI) tuning and Margin Optimization, DDR/MIPI/High Speed IO SerDes (PHY) design/validation, pre-/post-silicon verification. 
  • Extensive knowledge of the physical and protocol levels of latest industry standards of DDR4/5, LPDDR4/5, MIPI D-PHY/M-PHY.
  • Expertise in SI integrity measurements, equalization features validation and related tuning.
  • Experience in dealing directly with IP and DDR vendors/customers.
  • Customer-focused skills as a Hardware Application Engineer highly-desirable.
  • Experience in developing and testing DDR sub systems including working experience with DDR controller and PHY, JEDEC and DFI specifications
  • Microcontroller & Embedded Systems Programming Experience in C/C++
  • Understanding of ASIC/SOC boot flow and specifically DDR initialization process is highly desirable
  • Extensive experience with common lab equipment, including BERT, analyzers, oscilloscopes, PNA/VNA etc,.
  • Knowledge of High-speed analog and VLSI design, transmission-line theory.
  • Debug skills at both SoC and system level.
  • Strong programming/scripting skills (eg. Python, C/C++, Perl, TCL, Linux Sheel Script, etc.) for test methodology development and test automation
  • Excellent written and verbal interpersonal skills. Able to draft and manage technical documentations workflows such as Arch and uArch specs/user guides, with professional quality levels.

ACADEMIC CREDENTIALS:

  • Bachelors or Masters degree in computer engineering/Electrical Engineering

LOCATION:

Singapore

 

#LI-MM1

#LI-HYBRID

COMPANY JOBS
1694 available jobs
WEBSITE