SMTS Silicon Design Engineer (SOC design / Soc Integration Engineer with 10+Yrs)

May 29, 2024
Bengaluru, India
... Not specified
... Intermediate
Full time
... Office work


WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_




THE ROLE

  • Lead execution with SOC teams for Design.
  • Lead efficiency on execution of SOC for integration as well as various quality checks like lint, CDC, RDC, Synthesis, CLP, LEC, constraints quality checks.
  • Lead quality and timely delivery to various teams like DV, DFT, Emulation & PD.
  • Work with architecture team on high level arch and uArch definition.
  • Work with IP team for IP deliverables.
  • Work with SOC (Design, DFT, DV, PD), System and SW team to deliver next generation high performance SOC designs.
  • Work with post-Si team on Si bring up.
  • Suggest improvisation on methodologies in SOC design.
  • Has understanding on SOC and IP development milestones.

THE PERSON:

  • Good understanding of SOC design methodology & related flows. (Design integration including UPF, Lint, CDC, RDC, CLP, LEC). Also on various handoffs (DV, PD, DFT & Emulation)
  • Good interpersonal and stakeholders management skills.
  • Good problem-solving skills.
  • Detail-oriented candidate who can work seamlessly with SOC design team across geographies. Technical Leader with strong self-driving ability and winning attitude.
  • Should have excellent communication written, oral and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc.  

 

KEY RESPONSIBILITIES:

  • Lead part of SOC design execution.
  • Good understanding of sign-off flows like Lint, CDC, RDC, Formal Equivalence, Low Power Checks, timing convergence (both tile-level and FCT), and full chip integration flows.
  • Participate in methodology development ideas/forums.
  • Collaborate with CAD and EDA vendors to further strengthen AMD and S3 design methodology.
  • Strong interpersonal skills to work across teams in different geographies.
  • Provide technical suggestion, guidance, and Support to the engineering team. 

 

PREFERRED EXPERIENCE:

  • Expertise in SOC integration.
  • Work with a team of Architects, Hardware and Software engineers to define the High-Level Architecture.
  • Hands-on experience in different SOC design activities, Verification aspects, Debug/triage, bottleneck resolution etc. Strong Problem Solving and Debugging Skills
  • Comfortable with design/implementation tools and flows like VCS, SOC Connectivity, Spyglass Lint/CDC/RDC, VCLP, Synthesis – DC/FC, ICC, and Physical design implementation/signoff tools, STA and constraints analysis tools.
  • Understanding in SOC architecture, System bus and IO protocol understanding (e.g. AXI, PCIe, Memory, uProcessor, etc.)
  • Understanding of System integration, multi-die methodology, packaging, yield, and system solution.
  • Experience in working with SW team for BIOS, FW, Driver, SW stack, QA and SW release is a plus.
  • Good understanding of Power, Performance and Area (PPA) optimization techniques.
  • Good experience with Perl/TCL/Shell/Python scripting, and Verilog/VHDL RTL design.
  • Excellent presentation and inter-communication skills.

 

ACADEMIC CREDENTIALS:

  • ~12+ years of strong experience in SOC design and ASIC execution.
  • BE/B.Tech/ME/MTECH/MS or equivalent ECE/EEE with 8+ yrs. of experience

 

# LI-SR4




Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

THE ROLE

  • Lead execution with SOC teams for Design.
  • Lead efficiency on execution of SOC for integration as well as various quality checks like lint, CDC, RDC, Synthesis, CLP, LEC, constraints quality checks.
  • Lead quality and timely delivery to various teams like DV, DFT, Emulation & PD.
  • Work with architecture team on high level arch and uArch definition.
  • Work with IP team for IP deliverables.
  • Work with SOC (Design, DFT, DV, PD), System and SW team to deliver next generation high performance SOC designs.
  • Work with post-Si team on Si bring up.
  • Suggest improvisation on methodologies in SOC design.
  • Has understanding on SOC and IP development milestones.

THE PERSON:

  • Good understanding of SOC design methodology & related flows. (Design integration including UPF, Lint, CDC, RDC, CLP, LEC). Also on various handoffs (DV, PD, DFT & Emulation)
  • Good interpersonal and stakeholders management skills.
  • Good problem-solving skills.
  • Detail-oriented candidate who can work seamlessly with SOC design team across geographies. Technical Leader with strong self-driving ability and winning attitude.
  • Should have excellent communication written, oral and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc.  

 

KEY RESPONSIBILITIES:

  • Lead part of SOC design execution.
  • Good understanding of sign-off flows like Lint, CDC, RDC, Formal Equivalence, Low Power Checks, timing convergence (both tile-level and FCT), and full chip integration flows.
  • Participate in methodology development ideas/forums.
  • Collaborate with CAD and EDA vendors to further strengthen AMD and S3 design methodology.
  • Strong interpersonal skills to work across teams in different geographies.
  • Provide technical suggestion, guidance, and Support to the engineering team. 

 

PREFERRED EXPERIENCE:

  • Expertise in SOC integration.
  • Work with a team of Architects, Hardware and Software engineers to define the High-Level Architecture.
  • Hands-on experience in different SOC design activities, Verification aspects, Debug/triage, bottleneck resolution etc. Strong Problem Solving and Debugging Skills
  • Comfortable with design/implementation tools and flows like VCS, SOC Connectivity, Spyglass Lint/CDC/RDC, VCLP, Synthesis – DC/FC, ICC, and Physical design implementation/signoff tools, STA and constraints analysis tools.
  • Understanding in SOC architecture, System bus and IO protocol understanding (e.g. AXI, PCIe, Memory, uProcessor, etc.)
  • Understanding of System integration, multi-die methodology, packaging, yield, and system solution.
  • Experience in working with SW team for BIOS, FW, Driver, SW stack, QA and SW release is a plus.
  • Good understanding of Power, Performance and Area (PPA) optimization techniques.
  • Good experience with Perl/TCL/Shell/Python scripting, and Verilog/VHDL RTL design.
  • Excellent presentation and inter-communication skills.

 

ACADEMIC CREDENTIALS:

  • ~12+ years of strong experience in SOC design and ASIC execution.
  • BE/B.Tech/ME/MTECH/MS or equivalent ECE/EEE with 8+ yrs. of experience

 

# LI-SR4

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