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MTS SILICON DESIGN ENGINEER  

THE ROLE: 

The focus of this role is in developing clocking strategies that meet stringent timing, power, and area constraints while managing clock distribution across the SoC. 

THE PERSON:  

As the SoC Clock Design Lead, you will be responsible for the architecture, design, and optimization of clocking structures within complex SoCs. This position involves working closely with cross-functional teams, including RTL, physical design, power, and timing engineers, to ensure efficient and high-performance clock networks. 

KEY RESPONSIBILITIES:   

• Proficiency in clock tree synthesis (CTS) and clock network optimization using tools like Synopsys FC, ICC2.
• Strong experience in static timing analysis (STA), clock domain crossing (CDC) checks, and jitter/skew analysis.
• In-depth knowledge of clock gating, power optimization, and low-power design techniques.
• Strong scripting skills in Tcl, Perl, or Python for automation and flow enhancements
• Familiarity with advanced technology nodes (5nm and below) and their specific challenges in clock design
• Understanding of signal integrity, electromigration, and power integrity in the context of clock networks.

PREFERRED EXPERIENCE: 

• Define and implement the clock architecture and distribution strategy for SoCs, optimizing for performance, area, and power requirements.
• Lead clock tree synthesis, insertion, and optimization to achieve timing closure and reduce clock skew/jitter across the SoC.
• Implement and validate clock gating techniques to minimize dynamic power consumption and enhance SoC energy efficiency
• Work with RTL, timing, power, and PD teams to resolve clock-related issues, optimize clock distribution, and ensure alignment with SoC design goals
• Create and maintain custom scripts in Perl, Python, or Tcl to automate clocking tasks, streamline workflows, and improve productivity

ACADEMIC CREDENTIALS:  

Bachelors or Masters degree in computer engineering/Electrical Engineering.

#LI-PM2

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

MTS SILICON DESIGN ENGINEER  

THE ROLE: 

The focus of this role is in developing clocking strategies that meet stringent timing, power, and area constraints while managing clock distribution across the SoC. 

THE PERSON:  

As the SoC Clock Design Lead, you will be responsible for the architecture, design, and optimization of clocking structures within complex SoCs. This position involves working closely with cross-functional teams, including RTL, physical design, power, and timing engineers, to ensure efficient and high-performance clock networks. 

KEY RESPONSIBILITIES:   

• Proficiency in clock tree synthesis (CTS) and clock network optimization using tools like Synopsys FC, ICC2.
• Strong experience in static timing analysis (STA), clock domain crossing (CDC) checks, and jitter/skew analysis.
• In-depth knowledge of clock gating, power optimization, and low-power design techniques.
• Strong scripting skills in Tcl, Perl, or Python for automation and flow enhancements
• Familiarity with advanced technology nodes (5nm and below) and their specific challenges in clock design
• Understanding of signal integrity, electromigration, and power integrity in the context of clock networks.

PREFERRED EXPERIENCE: 

• Define and implement the clock architecture and distribution strategy for SoCs, optimizing for performance, area, and power requirements.
• Lead clock tree synthesis, insertion, and optimization to achieve timing closure and reduce clock skew/jitter across the SoC.
• Implement and validate clock gating techniques to minimize dynamic power consumption and enhance SoC energy efficiency
• Work with RTL, timing, power, and PD teams to resolve clock-related issues, optimize clock distribution, and ensure alignment with SoC design goals
• Create and maintain custom scripts in Perl, Python, or Tcl to automate clocking tasks, streamline workflows, and improve productivity

ACADEMIC CREDENTIALS:  

Bachelors or Masters degree in computer engineering/Electrical Engineering.

#LI-PM2