SoC Design For Test Engineer

Feb 04, 2024
Boston, United States
... Not specified
... Intermediate
Full time
... Office work


WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_




THE ROLE:

As a Design-for-Testability (DFT) engineer, you should have DFT end to end execution experience from DFT spec definition to post silicon bring up. You will meet regularly with other functional team members such as Architects, Verification Engineers, Physical Designers, CAD Engineers, SoC Design Engineers, Product Engineers and Program Management to ensure successful and timely project completion.

 

THE PERSON:

As a member of the Strategic Silicon Solutions (S3) Business Unit within AMD, your execution will help bring to life customers Special requirements for designs to be used in a broad range of products, from tablets to gaming consoles to servers and more. You will work closely with architecture, IP design, SoC implementation team, Design Verification team and physical design team to achieve first pass silicon success. You should be able to work efficiently within a team environment and drive tasks to completion, all while demonstrating excellent oral, written and interpersonal communication skills!

 

KEY RESPONSIBILITIES:

  • Implementation and verification of DFT architecture and features
  • Scan/Jtag/Boundary Scan insertion and ATPG pattern generation
  • Memory BIST logic generation, implementation and verification
  • Low power DFT
  • ATPG patterns verification, gate level simulation with timing
  • Test coverage and test cost reduction analysis
  • Post silicon support to ensure successful bringup and enhance yield learning

PREFERRED EXPERIENCE:

  • Understanding of Design For Test methodologies and DFT verification experience (eg. IEEE1500, JTAG 1149.x, scan, memory BIST, etc)
  • Experience with Tessent Testkompress and SSN
  • Experience with VCS simulation tool, Perl/Shell scripting and Verilog RTL design
  • Exposure to Static timing analysis & Timing closure
  • Pre-Silicon test planning & validation, engagement with Design teams
  • Characterization and debug of Scan/ATPG test in the new silicon designs and process technologies
  • Optimization of test flows for increased quality and cost improvement
  • Analysis of part failures leading to test coverage and yield improvement
  • Analysis of characterization data across PVT
  • Must have good communication skills and the ability to work in a worldwide team environment
  • Knowledge & experience of low power concepts, clock gating, power gating is a plus

ACADEMIC CREDENTIALS:  

  • BSEE/MSEE Electrical Engineering or Computer Engineering

 

 

#LI-TB1




At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

THE ROLE:

As a Design-for-Testability (DFT) engineer, you should have DFT end to end execution experience from DFT spec definition to post silicon bring up. You will meet regularly with other functional team members such as Architects, Verification Engineers, Physical Designers, CAD Engineers, SoC Design Engineers, Product Engineers and Program Management to ensure successful and timely project completion.

 

THE PERSON:

As a member of the Strategic Silicon Solutions (S3) Business Unit within AMD, your execution will help bring to life customers Special requirements for designs to be used in a broad range of products, from tablets to gaming consoles to servers and more. You will work closely with architecture, IP design, SoC implementation team, Design Verification team and physical design team to achieve first pass silicon success. You should be able to work efficiently within a team environment and drive tasks to completion, all while demonstrating excellent oral, written and interpersonal communication skills!

 

KEY RESPONSIBILITIES:

  • Implementation and verification of DFT architecture and features
  • Scan/Jtag/Boundary Scan insertion and ATPG pattern generation
  • Memory BIST logic generation, implementation and verification
  • Low power DFT
  • ATPG patterns verification, gate level simulation with timing
  • Test coverage and test cost reduction analysis
  • Post silicon support to ensure successful bringup and enhance yield learning

PREFERRED EXPERIENCE:

  • Understanding of Design For Test methodologies and DFT verification experience (eg. IEEE1500, JTAG 1149.x, scan, memory BIST, etc)
  • Experience with Tessent Testkompress and SSN
  • Experience with VCS simulation tool, Perl/Shell scripting and Verilog RTL design
  • Exposure to Static timing analysis & Timing closure
  • Pre-Silicon test planning & validation, engagement with Design teams
  • Characterization and debug of Scan/ATPG test in the new silicon designs and process technologies
  • Optimization of test flows for increased quality and cost improvement
  • Analysis of part failures leading to test coverage and yield improvement
  • Analysis of characterization data across PVT
  • Must have good communication skills and the ability to work in a worldwide team environment
  • Knowledge & experience of low power concepts, clock gating, power gating is a plus

ACADEMIC CREDENTIALS:  

  • BSEE/MSEE Electrical Engineering or Computer Engineering

 

 

#LI-TB1

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