WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_

THE ROLE:

The focus of this role is to plan, build, integrate and implement a large scale AMD’s graphics processor ASIC chip, resulting in no bugs in the final design. 

THE PERSON:  

You have a passion for modern, complex processor architecture, digital design and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.  

KEY RESPONSIBILITIES:

• Interact with SOC Design, DFT, and Verification teams and lead end-to-end SOC chip implementation.
• Work with different functional domain leads (FEI, PD, FCFP, FCT, CLOCK, PHYV) for large scale ASIC chip physical integration and implementation.
• Running regular execution meetings, scrums, standing meetings and resolving bottlenecks.
• Project planning, schedule, deliverables, risk and mitigations options. Presenting status updates.
• Coordinating and work with project execution teams across multiple geos worldwide.
• Work with program management team for IP requirement and deliverables.
• Work with program management team for SOC planning, schedule, resource demand/supply planning. 

PREFERRED EXPERIENCE:

• Experience of successfully leading SOC integration from RTL to GDSII.
• Expertise in SOC integration and implementation - IP Integration, SOC fabrics, Voltage and clock domain crossings, DFT, Power intent design, RTL Quality checks, Synthesis, Timing Analysis, Design Partitioning, PPA optimization, PnR, Timing analysis, FP convergence, Physical design implementation and signoff.
• Strong hands-on experience in different SOC design activities.
• Comfortable with design/implementation tools and flows like Spyglass Lint/CDC/RDC, SgLP, Synthesis – DC/FC, ICC, and Physical design implementation/signoff tools.
• Comfort with Scripting such as Perl, shell, Python and TCL is a plus.
• Understanding of System integration, multi-die methodology, packaging, and system solution.
• Expertise in managing execution team, project planning, IP delivery timelines, deliverables and quality checks, Resource planning, critical path analysis, risks and mitigation plan.
• Excellent communication and documentation skills.
• Leader with strong self-driving skills.
• Excellent communication skills, both written and oral.
• Strong leadership and proactive problem-solving skills

ACADEMIC CREDENTIALS:

• Bachelor's, Master, or PhD in Computer Science, Electrical Engineering or relevant fields. 

#LI-IA1

#LI-Hybrid

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

THE ROLE:

The focus of this role is to plan, build, integrate and implement a large scale AMD’s graphics processor ASIC chip, resulting in no bugs in the final design. 

THE PERSON:  

You have a passion for modern, complex processor architecture, digital design and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.  

KEY RESPONSIBILITIES:

• Interact with SOC Design, DFT, and Verification teams and lead end-to-end SOC chip implementation.
• Work with different functional domain leads (FEI, PD, FCFP, FCT, CLOCK, PHYV) for large scale ASIC chip physical integration and implementation.
• Running regular execution meetings, scrums, standing meetings and resolving bottlenecks.
• Project planning, schedule, deliverables, risk and mitigations options. Presenting status updates.
• Coordinating and work with project execution teams across multiple geos worldwide.
• Work with program management team for IP requirement and deliverables.
• Work with program management team for SOC planning, schedule, resource demand/supply planning. 

PREFERRED EXPERIENCE:

• Experience of successfully leading SOC integration from RTL to GDSII.
• Expertise in SOC integration and implementation - IP Integration, SOC fabrics, Voltage and clock domain crossings, DFT, Power intent design, RTL Quality checks, Synthesis, Timing Analysis, Design Partitioning, PPA optimization, PnR, Timing analysis, FP convergence, Physical design implementation and signoff.
• Strong hands-on experience in different SOC design activities.
• Comfortable with design/implementation tools and flows like Spyglass Lint/CDC/RDC, SgLP, Synthesis – DC/FC, ICC, and Physical design implementation/signoff tools.
• Comfort with Scripting such as Perl, shell, Python and TCL is a plus.
• Understanding of System integration, multi-die methodology, packaging, and system solution.
• Expertise in managing execution team, project planning, IP delivery timelines, deliverables and quality checks, Resource planning, critical path analysis, risks and mitigation plan.
• Excellent communication and documentation skills.
• Leader with strong self-driving skills.
• Excellent communication skills, both written and oral.
• Strong leadership and proactive problem-solving skills

ACADEMIC CREDENTIALS:

• Bachelor's, Master, or PhD in Computer Science, Electrical Engineering or relevant fields. 

#LI-IA1

#LI-Hybrid