WHAT YOU DO AT AMD CHANGES EVERYTHING
We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.
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SMTS SILICON DESIGN ENGINEER
THE ROLE:
We are currently looking for an experienced SoC Verification Engineer who will be part of a team working on next generation of complex AI/ML accelerator SoCs. The successful candidate will play a key technical role in SoC verification, defining verification strategies, authoring test plans, and executing those plans.
THE PERSON:
- Define verification plans for SoC designs using System Verilog with UVM and C++/DPI.
- Integrate verification IPs and construct new verification components in SoC environment
- Apply advanced verification techniques like constrained random generation, functional coverage, assertions, and formal verification to achieve successful tapeout metrics
- Write test cases, checkers, and coverage that implement the verification test plan.
- Provide technical leadership to junior engineers and interns
KEY RESPONSIBLITIES:
- Work with IP teams to define VIP deliverables, feature staging, and quality metrics per milestone
- Interact with a wide variety of internal and external design verification development teams, DV methodology teams, and tool vendors
- Work with hardware architecture and RTL designers to define test plans, coverage, and feature enablement
PREFERRED EXPERIENCE:
- Strong knowledge of SystemVerilog and UVM
- Strong knowledge of C/C++ and programming concepts like OOP, pointers, and polymorphism
- Strong knowledge of scripting languages preferred
- Strong understanding of computer architectures with topics such as memory management, cache coherency, and GPU designs is preferred
ACADEMIC CREDENTIALS:
- Bachelors or Masters degree in computer engineering/Electrical Engineering
#LI-CJ2
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
SMTS SILICON DESIGN ENGINEER
THE ROLE:
We are currently looking for an experienced SoC Verification Engineer who will be part of a team working on next generation of complex AI/ML accelerator SoCs. The successful candidate will play a key technical role in SoC verification, defining verification strategies, authoring test plans, and executing those plans.
THE PERSON:
- Define verification plans for SoC designs using System Verilog with UVM and C++/DPI.
- Integrate verification IPs and construct new verification components in SoC environment
- Apply advanced verification techniques like constrained random generation, functional coverage, assertions, and formal verification to achieve successful tapeout metrics
- Write test cases, checkers, and coverage that implement the verification test plan.
- Provide technical leadership to junior engineers and interns
KEY RESPONSIBLITIES:
- Work with IP teams to define VIP deliverables, feature staging, and quality metrics per milestone
- Interact with a wide variety of internal and external design verification development teams, DV methodology teams, and tool vendors
- Work with hardware architecture and RTL designers to define test plans, coverage, and feature enablement
PREFERRED EXPERIENCE:
- Strong knowledge of SystemVerilog and UVM
- Strong knowledge of C/C++ and programming concepts like OOP, pointers, and polymorphism
- Strong knowledge of scripting languages preferred
- Strong understanding of computer architectures with topics such as memory management, cache coherency, and GPU designs is preferred
ACADEMIC CREDENTIALS:
- Bachelors or Masters degree in computer engineering/Electrical Engineering
#LI-CJ2