WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_

THE ROLE 

The candidate will be a member of the PLL design team responsible for defining, specifying, and implementing future PLL IP. 

KEY RESPONSIBILITIES:   

• Lead and manage a team of PLL analog design engineers, including among others: tasks assignments and progress tracking, schedule and priority management, performance review, coaching and talent development, and hiring.
• Work closely with various disciplines (e.g. Layout, Logical Design, Physical Design, Firmware, and Design Verification) across different geographies and time zones, to ensure successful cross-team engagement and high-quality execution
• Ensure quality of deliverables within schedule and mitigate overall risk

• Participate and contribute to the definition of development flows that improve efficiency and quality of execution 
• Participate in definition of microarchitecture and in design implementation of various state-of-the-art, high-speed clocking analog/mixed-signal blocks for PLLs

 PREFERRED EXPERIENCE:

• A proven track record of managing/leading analog design teams and bringing development to production successfully

• A proven record of successful tape-outs in the area of high-speed analog design
• Strong/effective communication skills
• Enthusiastic team-first mentality
• Solid knowledge of industry-standard tools and best-in-class practices for analog/mixed-signal and high-speed designs
• Good knowledge in PLL and high-speed clocking design (signaling/equalization techniques, analog/mixed-signal circuit design, and signal integrity)
• Good knowledge in advanced, deep submicron semiconductor technologies (experience with FinFET technology is a plus)
• Analytical thinking and inventive spirit in combination with a solid understanding of risks and risk mitigation
• Familiarity with Perl, Python, and/or MATLAB
• Experience with Unix/Linux environments

ACADEMIC CREDENTIALS

• Electrical Engineering or Computer Engineering or related equivalent
• BS/ MS/ Ph.D.

LOCATION:  Santa Clara, CA

#LI-SL3

At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

THE ROLE 

The candidate will be a member of the PLL design team responsible for defining, specifying, and implementing future PLL IP. 

KEY RESPONSIBILITIES:   

• Lead and manage a team of PLL analog design engineers, including among others: tasks assignments and progress tracking, schedule and priority management, performance review, coaching and talent development, and hiring.
• Work closely with various disciplines (e.g. Layout, Logical Design, Physical Design, Firmware, and Design Verification) across different geographies and time zones, to ensure successful cross-team engagement and high-quality execution
• Ensure quality of deliverables within schedule and mitigate overall risk

• Participate and contribute to the definition of development flows that improve efficiency and quality of execution 
• Participate in definition of microarchitecture and in design implementation of various state-of-the-art, high-speed clocking analog/mixed-signal blocks for PLLs

 PREFERRED EXPERIENCE:

• A proven track record of managing/leading analog design teams and bringing development to production successfully

• A proven record of successful tape-outs in the area of high-speed analog design
• Strong/effective communication skills
• Enthusiastic team-first mentality
• Solid knowledge of industry-standard tools and best-in-class practices for analog/mixed-signal and high-speed designs
• Good knowledge in PLL and high-speed clocking design (signaling/equalization techniques, analog/mixed-signal circuit design, and signal integrity)
• Good knowledge in advanced, deep submicron semiconductor technologies (experience with FinFET technology is a plus)
• Analytical thinking and inventive spirit in combination with a solid understanding of risks and risk mitigation
• Familiarity with Perl, Python, and/or MATLAB
• Experience with Unix/Linux environments

ACADEMIC CREDENTIALS

• Electrical Engineering or Computer Engineering or related equivalent
• BS/ MS/ Ph.D.

LOCATION:  Santa Clara, CA

#LI-SL3