Sr. Manager Implementation Engineering

Aug 05, 2023
Hyderabad, India
... Not specified
... Senior
Full time
... Office work


WHAT YOU DO AT AMD CHANGES EVERYTHING

 

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

 

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Sr. Manager Implementation Engineering

 

THE ROLE:

 

The focus of this role in the AECG ASIC organization is to provide technical leadership in ASIC implementation & DFT, ensuring quality (design checks and verification reviews) and PD support for next generation ASICs.

 

THE PERSON:

 

You have a passion for modern, complex SoC architecture with various IO peripherals and heterogenous processor systems and digital design & verification in general. You are a team player who has excellent communication skills and experience collaborating in a corporate environment with other architects & engineers located in different sites/time-zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

 

KEY RESPONSIBILITIES: 

  • Lead Synthesis, DFT and other front end implementation functions in the development of next generation ASIC solutions and analyze implementation trade-offs
  • Align with company implementation flows for next-gen ASICs including processor system, IO Peripherals, platform management, interconnect, and memory subsystem
  • Lead internal and external teams to lead RTL->Netlist creation
  • Collaborate with marketing and program management to meet product requirements 
  • Work with other architects, design/verification, and software for IP development & acquisition

 

PREFERRED EXPERIENCE: 

  • Strong foundation in SoC architecture and processor systems with proven years of experience 
  • Good analytical problem solving, and attention to details
  • Excellent written and verbal communication skills
  • Knowledge of CPU, AXI Interconnect, and I/O peripherals
  • Knowledge of SOC development flow and accelerator IP
  • Must have worked with third party contractors
  • Should be an Expert with hands on experience in full chip or Subsystem timing closure, Low Power Synthesis, constraints development, DFT and other front end flows
  • Must have prior experience on ASIC physical design flows with various tools, understanding and scripting experience
  • Must have knowledge on RTL/design understanding, Synthesis optimization, SDC, clocking, low power (UPF) and DFT
  • Must have strong debugging skills- timing issues, SDC, clock propagation
  • Must have worked on multiple tapeouts and projects directly responsible for ASIC implementation
  • Experience with post-silicon bring-up is a plus

  

EDUCATION & EXPERIENCE: 

  • BS, MS or PhD degree in in Electrical Engineering or Computer Science. 10years of experience in an ASIC implementation role leading to an understanding of end-end development.

  

LOCATION:

Bangalore (preferred)

 

#LI-SR4




Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Sr. Manager Implementation Engineering

 

THE ROLE:

 

The focus of this role in the AECG ASIC organization is to provide technical leadership in ASIC implementation & DFT, ensuring quality (design checks and verification reviews) and PD support for next generation ASICs.

 

THE PERSON:

 

You have a passion for modern, complex SoC architecture with various IO peripherals and heterogenous processor systems and digital design & verification in general. You are a team player who has excellent communication skills and experience collaborating in a corporate environment with other architects & engineers located in different sites/time-zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

 

KEY RESPONSIBILITIES: 

  • Lead Synthesis, DFT and other front end implementation functions in the development of next generation ASIC solutions and analyze implementation trade-offs
  • Align with company implementation flows for next-gen ASICs including processor system, IO Peripherals, platform management, interconnect, and memory subsystem
  • Lead internal and external teams to lead RTL->Netlist creation
  • Collaborate with marketing and program management to meet product requirements 
  • Work with other architects, design/verification, and software for IP development & acquisition

 

PREFERRED EXPERIENCE: 

  • Strong foundation in SoC architecture and processor systems with proven years of experience 
  • Good analytical problem solving, and attention to details
  • Excellent written and verbal communication skills
  • Knowledge of CPU, AXI Interconnect, and I/O peripherals
  • Knowledge of SOC development flow and accelerator IP
  • Must have worked with third party contractors
  • Should be an Expert with hands on experience in full chip or Subsystem timing closure, Low Power Synthesis, constraints development, DFT and other front end flows
  • Must have prior experience on ASIC physical design flows with various tools, understanding and scripting experience
  • Must have knowledge on RTL/design understanding, Synthesis optimization, SDC, clocking, low power (UPF) and DFT
  • Must have strong debugging skills- timing issues, SDC, clock propagation
  • Must have worked on multiple tapeouts and projects directly responsible for ASIC implementation
  • Experience with post-silicon bring-up is a plus

  

EDUCATION & EXPERIENCE: 

  • BS, MS or PhD degree in in Electrical Engineering or Computer Science. 10years of experience in an ASIC implementation role leading to an understanding of end-end development.

  

LOCATION:

Bangalore (preferred)

 

#LI-SR4

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