Sr. Manager Silicon Design Engineering(181705)

Sep 09, 2022
Hyderabad, India
... Not specified
... Senior
Full time
... Office work


What you do at AMD changes everything 


At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 


Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

 

Masters or Bachelors in EE/ECE, 15+ years of relevant experience in VLSI domain.

 

As a senior manager, you would be managing and leading a team of fullchip STA engineers working on leading edge SOC products at AMD. The team is responsible for driving all fullchip timing closure activity on leading edge process nodes, as well as contributing significantly to STA methodology developments and improvements.  We are looking for an extremely strong technical leader who will guide and grow the team significantly.

 

Candidate would have solid understanding of complete ASIC PD/timing closure cycle, with extensive hands on experience leading teams on multiple proects on latest process nodes. Should be well versed in using industry standard STA tools like Primetime, PT based tcl scripting, as well as latest tools, mthodologies and techniques to drive timing closure in an efficient manner. Should have experience driving block and full-chip constraints development and providing guidance to RTL and PD teams to help close timing. Should understand the complete design cycle of modern SOC development, and be able to co-ordinate cross-functionally and cross-geographically to help drive the overall project execution across all design stages. Any hands-on with PNR would be very helpful. Strong understanding of Digital, CMOS, Crosstalk, OCV, IR-drop, EM, Process variations and other STA concepts. Should be able to drive the tem independently and completely own multiple critical products being developed in parallel. Strong verbal and written communication skills is a must. Should be a very good team player and be willing to contribute to cross functional and cross geographical team endeavors in terms of methodology and design process improvements.

 

#LN-SR4



Requisition Number: 181705 
Country/Region/Location: India State/Province: Telangana City: Hyderabad 
Job Function: 
Design  

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