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SENIOR SILICON DESIGN ENGINEER 

Job Description:

As a DFP, VSI, and UPF Specialist, you will drive the power management strategy, voltage scaling, and power intent development for System-on-Chip (SoC) designs. You will work closely with cross-functional teams to define and implement power-efficient designs using advanced low-power techniques, ensuring robust power and performance balance. Your expertise will be essential in implementing and verifying power intent using UPF, optimizing power domains, and managing voltage scaling and isolation strategies for complex SoCs.

Technical Requirements

• Expertise in UPF power intent formats and power-aware verification flows.
• Strong knowledge of DFP techniques, including power gating, multi-voltage, clock gating, and DVFS.
• Experience with VSI, power domain partitioning, and isolation cell management.
• Strong problem-solving, analytical, and communication skills. Ability to collaborate effectively across multiple teams and manage complex design requirements.

Responsibilities:

• Develop and optimize voltage scaling and isolation strategies across multiple power domains. Work with the physical design and RTL teams to ensure voltage islands and isolation cells meet design specifications.
• Create and maintain Unified Power Format (UPF) files to define power intent across the design. Ensure proper definition of power domains, retention, and power shutoff requirements to meet power integrity.
• Collaborate with the verification team to implement power-aware verification strategies using UPF, ensuring all power-related checks are met. Perform power analysis to identify potential issues and optimize the design.
• Work closely with the architecture, RTL, DFT, and physical design teams to integrate power management requirements, ensure alignment on power specifications, and resolve power-related issues.
• Document power management strategies, UPF implementation details, and analysis findings. Present findings and recommendations to design and management teams.
• Provide guidance and training to junior engineers and cross-functional teams on DFP, VSI, and UPF best practices and methodologies.

 #LI-SR4

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

SENIOR SILICON DESIGN ENGINEER 

Job Description:

As a DFP, VSI, and UPF Specialist, you will drive the power management strategy, voltage scaling, and power intent development for System-on-Chip (SoC) designs. You will work closely with cross-functional teams to define and implement power-efficient designs using advanced low-power techniques, ensuring robust power and performance balance. Your expertise will be essential in implementing and verifying power intent using UPF, optimizing power domains, and managing voltage scaling and isolation strategies for complex SoCs.

Technical Requirements

• Expertise in UPF power intent formats and power-aware verification flows.
• Strong knowledge of DFP techniques, including power gating, multi-voltage, clock gating, and DVFS.
• Experience with VSI, power domain partitioning, and isolation cell management.
• Strong problem-solving, analytical, and communication skills. Ability to collaborate effectively across multiple teams and manage complex design requirements.

Responsibilities:

• Develop and optimize voltage scaling and isolation strategies across multiple power domains. Work with the physical design and RTL teams to ensure voltage islands and isolation cells meet design specifications.
• Create and maintain Unified Power Format (UPF) files to define power intent across the design. Ensure proper definition of power domains, retention, and power shutoff requirements to meet power integrity.
• Collaborate with the verification team to implement power-aware verification strategies using UPF, ensuring all power-related checks are met. Perform power analysis to identify potential issues and optimize the design.
• Work closely with the architecture, RTL, DFT, and physical design teams to integrate power management requirements, ensure alignment on power specifications, and resolve power-related issues.
• Document power management strategies, UPF implementation details, and analysis findings. Present findings and recommendations to design and management teams.
• Provide guidance and training to junior engineers and cross-functional teams on DFP, VSI, and UPF best practices and methodologies.

 #LI-SR4