Sr. Silicon Design Engineer

May 15, 2024
Hsinchu, Taiwan
... Not specified
... Senior
Full time
... Office work


WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_




THE ROLE: 

AMD-AECG Package Development team is looking for a dynamic, competent Manager/Senior Staff package electrical design engineer to join our growing team. As a key contributor to the success of AMD’s FPGA product, you will be part of a leading team to drive and improve AMD’s abilities to deliver the highest quality, industry leading technologies to market. The Package Development team fosters and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.   

THE PERSON: 

The ideal candidate possesses an innovative and problem-solving mindset, has a keen eye for IC Package development, and is diligent and passionate about Technology. A successful candidate will need to employ strong knowledge in signal and power integrity of silicon and package design, leadership skills in technical areas, as well as a strong ability to compete effectively in a fast-paced, relevant environment while working with different teams of engineers and collaborators.  

  

KEY RESPONSIBILITIES:  

  • Perform package extraction for the time domain and frequency domain analysis  
  • Provide design guidelines for the Package design  
  • Power integrity analysis for state of art package/system designs, which include but not limited to package layout model extraction, transient noise analysis (ADS, HSPICE) to meet the silicon noise spec, decoupling strategy and analysis.   
  • SSN(Simultaneous Switching Noise) analysis for I/O (DDR5, LPDDR5, etc.) power domain.   
  • Eye diagram and jitter analysis for die-package-PCB co-simulations.  
  • Signal integrity simulation and optimization on package stack-up, power/ ground plane assignment and optimization, decoupling cap locations to minimize power ground noise.  
  • Opportunity to work on high speed and RF signal trace routing, via optimization, 
  • length matching and the impact to the timing.  
  • Crosstalk analysis and reduction on-package considering mutual-effect by on-die, on-silicon interposer and on-PCB.  
  • Full-wave modeling of vias, connectors, package and PCB channels, components using 3D full-wave EM tools. 

PREFERRED EXPERIENCE: 

  • Solid background on transmission-line theory and computational electromagnetics.  
  • Industry working experiences on signal integrity and power integrity in one or more of signaling standards, PCIe gen4/5, PAM4/8, Ethernet, DDR5, LPDDR5, HBM2/2e/3.  
  • Experiences with SI tools, HSPICE, HFSS/Q3D, PowerSI/PowerDC, ADS or similar.  
  • Hands-on lab experiences using high speed real time scope, VNA, TDR, and spectrum analyzer will be a plus.  
  • Familiar with RF designs, high speed package designs, or high speed PCB designs will be a plus.  
  • Knowledge and experience of on-die noise model will be a plus 

  

ACADEMIC CREDENTIALS: 

  • Master or Ph.D Degree in Electrical Engineering or Computer Science; experience desire

#LI-SC1




Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

THE ROLE: 

AMD-AECG Package Development team is looking for a dynamic, competent Manager/Senior Staff package electrical design engineer to join our growing team. As a key contributor to the success of AMD’s FPGA product, you will be part of a leading team to drive and improve AMD’s abilities to deliver the highest quality, industry leading technologies to market. The Package Development team fosters and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.   

THE PERSON: 

The ideal candidate possesses an innovative and problem-solving mindset, has a keen eye for IC Package development, and is diligent and passionate about Technology. A successful candidate will need to employ strong knowledge in signal and power integrity of silicon and package design, leadership skills in technical areas, as well as a strong ability to compete effectively in a fast-paced, relevant environment while working with different teams of engineers and collaborators.  

  

KEY RESPONSIBILITIES:  

  • Perform package extraction for the time domain and frequency domain analysis  
  • Provide design guidelines for the Package design  
  • Power integrity analysis for state of art package/system designs, which include but not limited to package layout model extraction, transient noise analysis (ADS, HSPICE) to meet the silicon noise spec, decoupling strategy and analysis.   
  • SSN(Simultaneous Switching Noise) analysis for I/O (DDR5, LPDDR5, etc.) power domain.   
  • Eye diagram and jitter analysis for die-package-PCB co-simulations.  
  • Signal integrity simulation and optimization on package stack-up, power/ ground plane assignment and optimization, decoupling cap locations to minimize power ground noise.  
  • Opportunity to work on high speed and RF signal trace routing, via optimization, 
  • length matching and the impact to the timing.  
  • Crosstalk analysis and reduction on-package considering mutual-effect by on-die, on-silicon interposer and on-PCB.  
  • Full-wave modeling of vias, connectors, package and PCB channels, components using 3D full-wave EM tools. 

PREFERRED EXPERIENCE: 

  • Solid background on transmission-line theory and computational electromagnetics.  
  • Industry working experiences on signal integrity and power integrity in one or more of signaling standards, PCIe gen4/5, PAM4/8, Ethernet, DDR5, LPDDR5, HBM2/2e/3.  
  • Experiences with SI tools, HSPICE, HFSS/Q3D, PowerSI/PowerDC, ADS or similar.  
  • Hands-on lab experiences using high speed real time scope, VNA, TDR, and spectrum analyzer will be a plus.  
  • Familiar with RF designs, high speed package designs, or high speed PCB designs will be a plus.  
  • Knowledge and experience of on-die noise model will be a plus 

  

ACADEMIC CREDENTIALS: 

  • Master or Ph.D Degree in Electrical Engineering or Computer Science; experience desire

#LI-SC1

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