Sr. Silicon Design Engineer

Apr 04, 2024
Hsinchu, Taiwan
... Not specified
... Senior
Full time
... Office work


WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

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SENIOR SILICON DESIGN ENGINEER 

 

THE ROLE:

 

It is a must that the candidate has one or more of the following experience/knowledge, such as X86/ARM/8051 architecture, AMBA(AXI/AHB/APB) bus, USB(3.0/2.0/1.1; HSIC/host/device/OTG) system, NAND Flash host controller/BCH/double-data-rate interface, PCI-E/PCI bus, low power design, clock generation and control, SD/eMMC host controller, SATA/SAS, Legacy IPs (SPI/SMBUS/ACPI/LPC/GPIO), General connectivity IPs (I2S/I2C/UART), Ethernet, JTAG, etc.

 

THE PERSON:

 

The candidate is expected to exhibit good verbal and written communication skills in both Chinese and English, specialized knowledge plus broad technical knowledge that facilitates integrative thinking, driving execution of quality and timely result, capability to solve complex, novel and no-recurring problems and decision-making on critical technical areas.

 

KEY RESPONSIBILITIES:

  • Work with team members and apply current functional verification techniques to perform and improve pre-silicon verification quality and product Time to Market for Southbridge
  • Provide the technical leadership to the DV team for the new Southbridge project
  • Work independently on various DV tasks and providing technical guidance to the DV team.
  • Be involved technically in the porting/creation of the DV environment for the new design, block and chip level test plan creation and implementation, coverage analysis, and regression cleanup

 

PREFERRED EXPERIENCE:

  • Master in Electrical Engineering, Computer Science or related
  • Good understanding on ASIC design verification flow
  • RTL coding with Verilog/System Verilog and familiar with front-end design flow and C/C++ programming experiences
  • Knowledge on Perl, OVL, SVA, SV, UVM, OVM, script programming etc.
  • USB experiences is a plus

 

ACADEMIC CREDENTIALS:

MSEE with minimum of 5 years, or BSEE with minimum of 7 years experiences in digital ASIC/SOC design verification

 

LOCATION:

 

Taipei/Hsinchu 

.

#LI-SC1 




Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

SENIOR SILICON DESIGN ENGINEER 

 

THE ROLE:

 

It is a must that the candidate has one or more of the following experience/knowledge, such as X86/ARM/8051 architecture, AMBA(AXI/AHB/APB) bus, USB(3.0/2.0/1.1; HSIC/host/device/OTG) system, NAND Flash host controller/BCH/double-data-rate interface, PCI-E/PCI bus, low power design, clock generation and control, SD/eMMC host controller, SATA/SAS, Legacy IPs (SPI/SMBUS/ACPI/LPC/GPIO), General connectivity IPs (I2S/I2C/UART), Ethernet, JTAG, etc.

 

THE PERSON:

 

The candidate is expected to exhibit good verbal and written communication skills in both Chinese and English, specialized knowledge plus broad technical knowledge that facilitates integrative thinking, driving execution of quality and timely result, capability to solve complex, novel and no-recurring problems and decision-making on critical technical areas.

 

KEY RESPONSIBILITIES:

  • Work with team members and apply current functional verification techniques to perform and improve pre-silicon verification quality and product Time to Market for Southbridge
  • Provide the technical leadership to the DV team for the new Southbridge project
  • Work independently on various DV tasks and providing technical guidance to the DV team.
  • Be involved technically in the porting/creation of the DV environment for the new design, block and chip level test plan creation and implementation, coverage analysis, and regression cleanup

 

PREFERRED EXPERIENCE:

  • Master in Electrical Engineering, Computer Science or related
  • Good understanding on ASIC design verification flow
  • RTL coding with Verilog/System Verilog and familiar with front-end design flow and C/C++ programming experiences
  • Knowledge on Perl, OVL, SVA, SV, UVM, OVM, script programming etc.
  • USB experiences is a plus

 

ACADEMIC CREDENTIALS:

MSEE with minimum of 5 years, or BSEE with minimum of 7 years experiences in digital ASIC/SOC design verification

 

LOCATION:

 

Taipei/Hsinchu 

.

#LI-SC1 

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