Sr. Silicon Design Engineer

Feb 13, 2024
Hyderabad, India
... Not specified
... Senior
Full time
... Office work


WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_




 

 

MTS SILICON DESIGN ENGINEER  

  

THE ROLE: 

The focus of this role is to do Synthesis on Multi Million gates with complex Power in lower Technology Nodes for AMD’s Server SOC, resulting in good PPA

  

THE PERSON:  

You have a passion in debugging the complex logic to meet PPA requirements and to do signoff for Timing, LEC and VSI. You are a team lead who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. 

  

KEY RESPONSIBILITIES:  

  • Synthesize Multi Million gate design to meet Timing, Power and Area
  • Logical Equivalence check need to be done at different stages in the Flow
  • Understand the power architecture and write the UPF
  • Power architecture implemented on Netlist need be verified by VSI
  • Understand the Clock architecture and need to write the SDC
  • Able to write the Functional ECO’s and Implement ECO’s using CECO
  • Will be interacting to PD and Design team for Design Closure

 

PREFERRED EXPERIENCE:  

  • 8 to 12 year experience in Synthesis handling Complex Blocks for power aware designs
  • Able to lead the team of 10+ Engineers  
  •  Good Knowledge in Verilog
  • Strong debug skills and experience with Conformal/Formality for LEC
  • Experience with VSI in signoff for power aware checks
  • Strong Knowledge On timing Concepts
  • Good knowledge on Scan and PNR
  • Hands on Experience on EDA tools Design compiler, Fusion Compiler, Prime Time, Verdi , Formality, Conformal
  • Experience with any scripting languages like Tcl/Perl/Ruby/Python

 

  

ACADEMIC CREDENTIALS:  

  • Bachelors or Masters degree in Electronics engineering/Electrical Engineering 

 

#LI-PK1

 




Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

 

 

MTS SILICON DESIGN ENGINEER  

  

THE ROLE: 

The focus of this role is to do Synthesis on Multi Million gates with complex Power in lower Technology Nodes for AMD’s Server SOC, resulting in good PPA

  

THE PERSON:  

You have a passion in debugging the complex logic to meet PPA requirements and to do signoff for Timing, LEC and VSI. You are a team lead who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. 

  

KEY RESPONSIBILITIES:  

  • Synthesize Multi Million gate design to meet Timing, Power and Area
  • Logical Equivalence check need to be done at different stages in the Flow
  • Understand the power architecture and write the UPF
  • Power architecture implemented on Netlist need be verified by VSI
  • Understand the Clock architecture and need to write the SDC
  • Able to write the Functional ECO’s and Implement ECO’s using CECO
  • Will be interacting to PD and Design team for Design Closure

 

PREFERRED EXPERIENCE:  

  • 8 to 12 year experience in Synthesis handling Complex Blocks for power aware designs
  • Able to lead the team of 10+ Engineers  
  •  Good Knowledge in Verilog
  • Strong debug skills and experience with Conformal/Formality for LEC
  • Experience with VSI in signoff for power aware checks
  • Strong Knowledge On timing Concepts
  • Good knowledge on Scan and PNR
  • Hands on Experience on EDA tools Design compiler, Fusion Compiler, Prime Time, Verdi , Formality, Conformal
  • Experience with any scripting languages like Tcl/Perl/Ruby/Python

 

  

ACADEMIC CREDENTIALS:  

  • Bachelors or Masters degree in Electronics engineering/Electrical Engineering 

 

#LI-PK1

 

COMPANY JOBS
1746 available jobs
WEBSITE