Sr. Silicon Design Engineer

Feb 07, 2024
Markham, Canada
... Not specified
... Senior
Full time
... Office work

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_


Responsibilities

SENIOR SILICON DESIGN ENGINEER 

 

THE ROLE:

The SOC RTG team develops leading edge discrete graphics SOCs. The team owns SOC execution and is actively engaged from architecture to production. Working as part of the SOC leadership team, candidates will gain knowledge in system and IP level design, SOC architecture and implementation strategies.

THE PERSON:

  • Must have good communication & analytical thinking skills
  • Detail oriented with strong analytical and debugging skills

KEY RESPONSIBILITIES:

  • Integrate AMD internal IPs RTL/DV environments into SoC
  • Debug function/performance of Graphics, Display, Data Fabric, SMU IPs
  • Engage with IP and SOC teams to drive closure to IP RTL quality metrics (ie: area, timing, DFP, LINT, CDC)
  • Work with global Front-End design team and physical design team for large scale ASIC chip physical implementation
  • Drive design and methodology improvements across teams to improve overall program execution
  • Participate in defining and implementing the design power-intent (power-gating / voltage islands)

PREFERRED EXPERIENCE:

  • Proficiency with Verilog RTL design languages
  • ASIC DV experience in reusable verification methodology such as UVM
  • Knowledge of chip bus interfaces such as AHB,AXI and various standard peripherals & interfaces is a plus
  • Have hands-on experience in chip level Design/Integration activities
  • Have in depth knowledge of entire design process from design specification, defining architecture, micro-architecture, RTL design and functional verification, Synthesis, Physical Design, Timing closure, Tape-out, and post-Si debug
  • Some exposure to DFT is a strong plus

ACADEMIC CREDENTIALS:

  • Bachelor or Masters Degree in Electrical Engineering, Computer Engineering or Computer Science.

 

 

#LI-PH1


Qualifications

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

SENIOR SILICON DESIGN ENGINEER 

 

THE ROLE:

The SOC RTG team develops leading edge discrete graphics SOCs. The team owns SOC execution and is actively engaged from architecture to production. Working as part of the SOC leadership team, candidates will gain knowledge in system and IP level design, SOC architecture and implementation strategies.

THE PERSON:

  • Must have good communication & analytical thinking skills
  • Detail oriented with strong analytical and debugging skills

KEY RESPONSIBILITIES:

  • Integrate AMD internal IPs RTL/DV environments into SoC
  • Debug function/performance of Graphics, Display, Data Fabric, SMU IPs
  • Engage with IP and SOC teams to drive closure to IP RTL quality metrics (ie: area, timing, DFP, LINT, CDC)
  • Work with global Front-End design team and physical design team for large scale ASIC chip physical implementation
  • Drive design and methodology improvements across teams to improve overall program execution
  • Participate in defining and implementing the design power-intent (power-gating / voltage islands)

PREFERRED EXPERIENCE:

  • Proficiency with Verilog RTL design languages
  • ASIC DV experience in reusable verification methodology such as UVM
  • Knowledge of chip bus interfaces such as AHB,AXI and various standard peripherals & interfaces is a plus
  • Have hands-on experience in chip level Design/Integration activities
  • Have in depth knowledge of entire design process from design specification, defining architecture, micro-architecture, RTL design and functional verification, Synthesis, Physical Design, Timing closure, Tape-out, and post-Si debug
  • Some exposure to DFT is a strong plus

ACADEMIC CREDENTIALS:

  • Bachelor or Masters Degree in Electrical Engineering, Computer Engineering or Computer Science.

 

 

#LI-PH1

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