Sr. Silicon Design Engineer (PNR design / Physical Design Engineer with 5+Yrs )

Apr 05, 2024
Hyderabad, India
... Not specified
... Senior
Full time
... Office work


WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_




SENIOR SILICON DESIGN ENGINEER 

 

 

 As part of the AECG integration team, the candidate will be involved in different phases of Tile/block Physical implementation starting from RTL to final GDSII.

 

Job Requirements:  

    1. Master’s/Bachelor’s degree in Electrical/Electronics engineering with 3 to 5 years of experience in semi-custom or PNR design
    2. Must be a good team player with good oral and written communication skills
    3. Expertise in physical implementation of digital blocks using industry standard Automatic Palace and Route (APR) Tools meeting PPA spec
    4. Expertise in floorplanning including power grid design to meet EMIR specifications
    5. Excellent understanding of timing concepts and signoff
    6. Hands on experience in Generating and Implementing ECOs to fix timing, noise and EMIR violations
    7. Good hands on experience in analyzing and fixing physical DRCs and analyzing LVS issues in Calibre tool
    8. Participate and contribute in enhancing physical design methodologies and flows
    9. Excellent scripting skills in tcl/perl and scripting savvy
    10. A good understanding of electrical, timing and reliability issues in deep sub micron circuit design.

#LI-SR4




Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

SENIOR SILICON DESIGN ENGINEER 

 

 

 As part of the AECG integration team, the candidate will be involved in different phases of Tile/block Physical implementation starting from RTL to final GDSII.

 

Job Requirements:  

    1. Master’s/Bachelor’s degree in Electrical/Electronics engineering with 3 to 5 years of experience in semi-custom or PNR design
    2. Must be a good team player with good oral and written communication skills
    3. Expertise in physical implementation of digital blocks using industry standard Automatic Palace and Route (APR) Tools meeting PPA spec
    4. Expertise in floorplanning including power grid design to meet EMIR specifications
    5. Excellent understanding of timing concepts and signoff
    6. Hands on experience in Generating and Implementing ECOs to fix timing, noise and EMIR violations
    7. Good hands on experience in analyzing and fixing physical DRCs and analyzing LVS issues in Calibre tool
    8. Participate and contribute in enhancing physical design methodologies and flows
    9. Excellent scripting skills in tcl/perl and scripting savvy
    10. A good understanding of electrical, timing and reliability issues in deep sub micron circuit design.

#LI-SR4

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