Sr. Silicon Design Engineer

Sep 11, 2022
San Jose, Philippines
... Not specified
... Senior
Full time
... Office work

What you do at AMD changes everything 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

Sr. Silicon Design Engineer

The Role

AMD is seeking an experienced front-end implementation engineer for the development and silicon verification of high-performance IP blocks in the company’s next generation products.  Successful candidates will be responsible for prototype implementation of assigned IP blocks to ensure RTL meets all defined quality metrics.  The other responsibilities will include implementation of system level design in FPGA using different FPGA IP blocks which meets the front-end design criteria and use the design to test the silicon on Bench or ATE tester. As a member of the Hard IP Design group, you will work on both design flow automation, VIVADO SW flow and product implementation and silicon verification groups.   Close interaction with both the RTL design team, VIVADO SW team is essential.  

The Person

The type of person who will be successful in this role is highly inquisitive, a team player, communicates proactively, has excellent written and verbal communication skills, and is highly analytical.

Applicants should possess a BS/MS in EE or equivalent field with applicable work experience in the several of the following tools. The position requires substantial TCL-based scripting competence within CAD tool shell environments as well as stand-alone TCL shell scripts. Prior work experience in FPGA design using VIVADO tool and silicon testing is required.

Key Responsibilities:

  • Implement IP in FPGA environment using Vivado or similar tools/flows
  • Implement IP in ASIC flow using System Verilog
  • Complete physical implementation using Synthesis and Place and Route tools
  • Develop SDC constraint and do timing analysis using Prime Time or equivalent timing analysis tool
  • Run static checks using LINT, LEC, CDC
  • Support RTL functional simulation and verification
  • Improve the efficiency and quality using scripting and programming
  • Support Silicon testing on bench or ATE tester
  • Support SW modelling of the IP block

Preferred Experience in following tools/flows

  • Experience working in a Unix/Linux environment.
  • Virtuoso tools for schematic
  • Perl/Python/C++ scripting and programming
  • Debug tools or waveform viewers

Academic Credentials

  • BS/MS (Computer Science, Computer Engineering, Electrical Engineering, or related equivalent) 

San Jose, CA, USA



Requisition Number: 180663 
Country: United States State: California City: San Jose 
Job Function: Design

Benefits offered are described here.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

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