Sr. Silicon Design Engineer

May 19, 2022
Shanghai, China
... Not specified
... Senior
Full time
... Office work

What you do at AMD changes everything 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.


MPME PV Engineer



MPME: Multi-sybsystem interoperability, Performance verification and architecture Modeling, Emulation

AMD NBIO (North Bridge IO) team delivers industry leading high-performance interconnects IP for all AMD products including dGPU, APU, Server and Game consoles. NBIO global operates seamless from China, North America and Europe.

As a global team, the candidate also has opportunities to travel to Canada, Serbia or America to attend some technique conferences, face to face to talk with global technique leads.



Be good at communication and teamwork, self-motivated and with good work ethics.



  • NBIO subsystem performance verification.
  • Work with global/local IP architects/designers to get a thorough understanding about each IP within NBIO container, like PCIe, IOHUB, nBIF/SHUB and DMA accelerator.
  • Develop NBIO PV test plan and testcase. Debug performance bottleneck and latency analysis.
  • Work with global/local IP PV teams and System Performance Groups, to achieve NBIO PV excellence. 



  • Complex IP Design Verification, direct experience in IP/SOC or Processor (CPU or GPU).
  • Good knowledge of design verification methodology, familiar with UVM/OVM/VMM.
  • Good RTL coding with Verilog, test-bench coding with SystemVerilog.
  • Hands on experience of PCIe verification is a strong plus.
  • Have performance verification experience is a strong plus.
  • Have leading edge industrial high speed I/O verification, like CXL and USB4 is a strong plus.
  • Be good at script language, such as Perl, Python, Ruby, C Shell, Makefile.
  • Be good at both speaking and written English.



  • MSEE within 2-5 years, or BSEE within 3-7 years’ experience in digital ASIC/SOC design verification




Requisition Number: 161287 
Country/Region/Location: China State/Province: Shanghai City: Shanghai 
Job Function: 

5000 + employees
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