Sr. Silicon Design Engineer

Nov 24, 2023
Shanghai, China
... Not specified
... Senior
Full time
... Office work


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We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

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SENIOR SILICON DESIGN ENGINEER 

  

THE ROLE: 

AMD SCBU team is the Semi-Customized Unit. We design the APUs mainly for consoles. Design Verification team is part of the whole chip design team and responsible to make sure the RTL quality. You will be working with DFT design and front-end team to verify the debug logic and make sure it is working on post-Si.

THE PERSON:

A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills.

KEY RESPONSIBLITIES:

  • Implementation and verification of DFT architecture and features 
  • Scan insertion and ATPG pattern generation 
  • ATPG patterns verification with gate-level simulation 
  • Test coverage and test cost reduction analysis 
  • Post silicon support to ensure successful bring up and enhance yield learning
  • Proficient in one kind of simulation tool like VCS, have good debug skill.
  • Familiar with SystemVerilog/C/C++ language.
  • Have the knowledge for UVM.
  • Familiar with script language like SHELL/Perl/Python.


P
REFERRED EXPERIENCE:

  • Understanding of Design for Test methodologies and DFT verification experience (eg. IEEE1500, JTAG 1149.x, Scan, memory BIST etc.) 
  • Experience with Mentor testkompress and/or Synopsys Tetramax/DFTMAX 
  • Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design 

 

 

ACADEMIC CREDENTIALS:

  • Bachelors or Masters degree in computer engineering/Electrical Engineering 

 

LOCATION:

Shanghai

 

#LI-VC1




Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

SENIOR SILICON DESIGN ENGINEER 

  

THE ROLE: 

AMD SCBU team is the Semi-Customized Unit. We design the APUs mainly for consoles. Design Verification team is part of the whole chip design team and responsible to make sure the RTL quality. You will be working with DFT design and front-end team to verify the debug logic and make sure it is working on post-Si.

THE PERSON:

A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills.

KEY RESPONSIBLITIES:

  • Implementation and verification of DFT architecture and features 
  • Scan insertion and ATPG pattern generation 
  • ATPG patterns verification with gate-level simulation 
  • Test coverage and test cost reduction analysis 
  • Post silicon support to ensure successful bring up and enhance yield learning
  • Proficient in one kind of simulation tool like VCS, have good debug skill.
  • Familiar with SystemVerilog/C/C++ language.
  • Have the knowledge for UVM.
  • Familiar with script language like SHELL/Perl/Python.


P
REFERRED EXPERIENCE:

  • Understanding of Design for Test methodologies and DFT verification experience (eg. IEEE1500, JTAG 1149.x, Scan, memory BIST etc.) 
  • Experience with Mentor testkompress and/or Synopsys Tetramax/DFTMAX 
  • Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design 

 

 

ACADEMIC CREDENTIALS:

  • Bachelors or Masters degree in computer engineering/Electrical Engineering 

 

LOCATION:

Shanghai

 

#LI-VC1

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