Sr. Sys/Test Validation Engineer

Apr 04, 2024
Shanghai, China
... Not specified
... Senior
Full time
... Office work


WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

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THE ROLE:

This technical role is for AMD DGPU paring validation in Client team. The individual will be responsible for DGPU paring test strategy definition, DGPU paring test plan creation, test execution, issue debug and drive for product on time delivery.  The individual will co-work with Driver, Debug, Validation IP owners and Platform Design teams to develop, optimize and execute DGPU paring validation test plans.

 

THE PERSON:

The person needs to be well self-motivated for deliveries and innovation. Good experience in GFX/DCN validation/debug.  A quick learner for new technologies and good communication skills.

 

KEY RESPONSIBILITIES:

  • Drive DGPU paring validation, including A+A and A+N 
  • AAA feature enablement/validation/debug
  • Work with cross-functional teams to improve AAA test strategy, methodology, and process
  • Develop, optimize, and execute DGPU paring validation test plans
  • Develop validation infrastructure and improve execution efficiency (hardware, automation environment …)
  • Issue reporting and work with other teams for issue analysis/ debug/ root cause/implement verify.
  • Work in a high demand, fast-paced environment with lots of real-time problem solving and critical thinking
  • Predicate execution risks and provide migration risk plan

 

REQUIRED EXPERIENCE:

  • Knowledge of computer hardware architecture and windows OS
  • Good knowledge of HG technology and AAA features
  • Good Knowledge of GFX and DCN
  • Experience developing validation methodologies and infrastructure for DGPU paring test.
  • Able to execute and drive success of programs with multiple projects on the go
  • Debug skills at both IP and system levels.
  • Must be a self-starting team player with excellent verbal and written English communication skills.
  • Forward thinker to improve process and drive innovation.
  • EE experience preferred.

 

PREFERRED EXPERIENCE:

  • Working knowledge of lab equipment
  • Self-organizing and the ability multitask based on priorities.
  • Scripting and automation tool development is a plus.
  • Linux environment validation or development experience is also a great plus.

 

  ACADEMIC CREDENTIALS:

  • Bachelor with 3+ years’ experience.

 

 

LOCATION:

Shanghai

 

#LI-ML5

 




Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

 

 

THE ROLE:

This technical role is for AMD DGPU paring validation in Client team. The individual will be responsible for DGPU paring test strategy definition, DGPU paring test plan creation, test execution, issue debug and drive for product on time delivery.  The individual will co-work with Driver, Debug, Validation IP owners and Platform Design teams to develop, optimize and execute DGPU paring validation test plans.

 

THE PERSON:

The person needs to be well self-motivated for deliveries and innovation. Good experience in GFX/DCN validation/debug.  A quick learner for new technologies and good communication skills.

 

KEY RESPONSIBILITIES:

  • Drive DGPU paring validation, including A+A and A+N 
  • AAA feature enablement/validation/debug
  • Work with cross-functional teams to improve AAA test strategy, methodology, and process
  • Develop, optimize, and execute DGPU paring validation test plans
  • Develop validation infrastructure and improve execution efficiency (hardware, automation environment …)
  • Issue reporting and work with other teams for issue analysis/ debug/ root cause/implement verify.
  • Work in a high demand, fast-paced environment with lots of real-time problem solving and critical thinking
  • Predicate execution risks and provide migration risk plan

 

REQUIRED EXPERIENCE:

  • Knowledge of computer hardware architecture and windows OS
  • Good knowledge of HG technology and AAA features
  • Good Knowledge of GFX and DCN
  • Experience developing validation methodologies and infrastructure for DGPU paring test.
  • Able to execute and drive success of programs with multiple projects on the go
  • Debug skills at both IP and system levels.
  • Must be a self-starting team player with excellent verbal and written English communication skills.
  • Forward thinker to improve process and drive innovation.
  • EE experience preferred.

 

PREFERRED EXPERIENCE:

  • Working knowledge of lab equipment
  • Self-organizing and the ability multitask based on priorities.
  • Scripting and automation tool development is a plus.
  • Linux environment validation or development experience is also a great plus.

 

  ACADEMIC CREDENTIALS:

  • Bachelor with 3+ years’ experience.

 

 

LOCATION:

Shanghai

 

#LI-ML5

 

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