STA/FEINT Design Engineer

May 23, 2024
Santa Clara, Cuba
... Not specified
... Intermediate
Full time
... Office work


WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_




THE ROLE: 

The STA/Constraints Engineer is responsible for developing FullChip constraints and timing closure. They will work closely with Fellows, Principal Engineers, Architects, collaborate with cross functional worldwide teams across Physical Design, Timing Analysis, Synthesis, Physical Verification, Power signoff, and mentor/coach/guide Design Engineers.

 

KEY RESPONSIBILITIES:  

  • Lead the full chip timing team for constraints and timing signoff.
  • Own end-to-end delivery of designs (SOC and Sub-system integration) from timing constraints and timing signoff perspective.
  • Work closely with the SOC Architecture team for SOC clocks & STA for statistical timing target goals.
  • Understanding clock design requirements and making sure they are correctly set up in SDC.
  • Understand timing margins (LVF/SSTA/Variations etc.) on the latest tech nodes and work with timing methodology teams for future and current projects.
  • Understand design requirements, timelines and various milestones of a project and deliver FCT closure accordingly.
  • Lead the timing ECO phase and plan for on-time project tape out.
  • Collaborate with CAD and EDA vendors to further strengthen AMD timing closure and constraints methodology.
  • Responsible for cdc/lint, timing closure, lower power implementation and netlist quality check with RTL designer and PD team.
  • Work on SDC development, STA (Static Timing)  analysis, shift left of timing closure, CDC (Clock Domain Crossing).
  •  

PREFERRED EXPERIENCE:  

  • Experienced PD professional with industry experience in STA, constraints, timing signoff and physical design
  • Expert user of industry-standard PD tools like SNPS PT/GCA (must) and ICC2/FC (desired).
  • Good experience and understanding of DFT timing concepts, MBIST, Top level clock -implementation, Place and Route flows -floorplanning and placement, CTS and Route. 
  • Good experience with Perl/TCL/Shell/Python scripting, and Verilog RTL design.
  • Excellent presentation and inter-communication skills.
  • Experience with Verilog RTL design/implementation and has experience of large digital ASIC project.
  • Experience with physical design is a plus.
  • Has Synthesis or physical implement experience.
  • Experience with lower power design methodology.

ACADEMIC CREDENTIALS:  

    • Bachelor/Master’s degree in Micro Electronics/ Integrated Circuit Science, or related field preferred.

#LI-PA1




At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

THE ROLE: 

The STA/Constraints Engineer is responsible for developing FullChip constraints and timing closure. They will work closely with Fellows, Principal Engineers, Architects, collaborate with cross functional worldwide teams across Physical Design, Timing Analysis, Synthesis, Physical Verification, Power signoff, and mentor/coach/guide Design Engineers.

 

KEY RESPONSIBILITIES:  

  • Lead the full chip timing team for constraints and timing signoff.
  • Own end-to-end delivery of designs (SOC and Sub-system integration) from timing constraints and timing signoff perspective.
  • Work closely with the SOC Architecture team for SOC clocks & STA for statistical timing target goals.
  • Understanding clock design requirements and making sure they are correctly set up in SDC.
  • Understand timing margins (LVF/SSTA/Variations etc.) on the latest tech nodes and work with timing methodology teams for future and current projects.
  • Understand design requirements, timelines and various milestones of a project and deliver FCT closure accordingly.
  • Lead the timing ECO phase and plan for on-time project tape out.
  • Collaborate with CAD and EDA vendors to further strengthen AMD timing closure and constraints methodology.
  • Responsible for cdc/lint, timing closure, lower power implementation and netlist quality check with RTL designer and PD team.
  • Work on SDC development, STA (Static Timing)  analysis, shift left of timing closure, CDC (Clock Domain Crossing).
  •  

PREFERRED EXPERIENCE:  

  • Experienced PD professional with industry experience in STA, constraints, timing signoff and physical design
  • Expert user of industry-standard PD tools like SNPS PT/GCA (must) and ICC2/FC (desired).
  • Good experience and understanding of DFT timing concepts, MBIST, Top level clock -implementation, Place and Route flows -floorplanning and placement, CTS and Route. 
  • Good experience with Perl/TCL/Shell/Python scripting, and Verilog RTL design.
  • Excellent presentation and inter-communication skills.
  • Experience with Verilog RTL design/implementation and has experience of large digital ASIC project.
  • Experience with physical design is a plus.
  • Has Synthesis or physical implement experience.
  • Experience with lower power design methodology.

ACADEMIC CREDENTIALS:  

    • Bachelor/Master’s degree in Micro Electronics/ Integrated Circuit Science, or related field preferred.

#LI-PA1

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