Video IP Integration Engineer - Contract

Mar 29, 2024
Markham, Canada
... Not specified
... Intermediate
Contract
... Office work


WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

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THE ROLE: 

We, Video HW IP/Solution Group at AMD Markham site, are looking for a Video IP Integration Engineer - Contract   who will work in an established IP team. The role will require the candidate to initially acquire background knowledge of VCN IP core, synthesis, timing, CDC, RDC, STA methodologies. Subsequently, the candidate will be responsible to enable different SoCs activities within IP delivery/SoC FEINT team. In addition, the engineer will work with IP developers for SoC integration, synthesis and timing issues.

 

THE PERSON: 

Will collaborate with the Video IP development team and SoC teams to produce forward-thinking integration for state of the art designs. With your analytical mind, you will be problem-solving in a fast-paced work environment for SoC integration issues. If you possess the ability to adapt quickly to rapid technology changes you will excel at AMD.

 

KEY RESPONSIBILITIES:

  • Collaborate with global IP development teams on SoC integration, IP release flow, IP quality checks for SoCs including running synthesis for different tech nodes, timing, STA, CDC, RDC issues
  • Create IP/SoC specific memory generation, synthesis runs and timing checks.
  • Develop CDC, RDC flows and work with IP design team to resolve issues at IP and SoC level.
  • Work with SoC teams to address IP issues related to synthesis, timing, STA, CDC, Lint and RDC issues.
  • Work with SoC PD teams to close timing at IP and chip level.

 

EXPERIENCE REQUIREMENTS:

  • Proficient in SoC/IP integration, Synthesis, STA checks and SoC FEINT flows.
  • 6+ years of hands-on RTL design synthesis and integration experience in ASIC product development.
  • Strong RTL design experience.
  • Proficient in System Verilog, Understanding of UVM test benches and scripting languages (csh, perl, Python, etc.).
  • Proficient in SoC level timing closure, LEC failure debugging, understanding of Synthesis, lint and CDC flows/tools.
  • Need to mentor junior engineers and take IP leadership role within SoC groups.

 

ACADEMIC CREDENTIALS: 

  • Bachelors or Masters degree in computer engineering/Electrical Engineering 



Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

THE ROLE: 

We, Video HW IP/Solution Group at AMD Markham site, are looking for a Video IP Integration Engineer - Contract   who will work in an established IP team. The role will require the candidate to initially acquire background knowledge of VCN IP core, synthesis, timing, CDC, RDC, STA methodologies. Subsequently, the candidate will be responsible to enable different SoCs activities within IP delivery/SoC FEINT team. In addition, the engineer will work with IP developers for SoC integration, synthesis and timing issues.

 

THE PERSON: 

Will collaborate with the Video IP development team and SoC teams to produce forward-thinking integration for state of the art designs. With your analytical mind, you will be problem-solving in a fast-paced work environment for SoC integration issues. If you possess the ability to adapt quickly to rapid technology changes you will excel at AMD.

 

KEY RESPONSIBILITIES:

  • Collaborate with global IP development teams on SoC integration, IP release flow, IP quality checks for SoCs including running synthesis for different tech nodes, timing, STA, CDC, RDC issues
  • Create IP/SoC specific memory generation, synthesis runs and timing checks.
  • Develop CDC, RDC flows and work with IP design team to resolve issues at IP and SoC level.
  • Work with SoC teams to address IP issues related to synthesis, timing, STA, CDC, Lint and RDC issues.
  • Work with SoC PD teams to close timing at IP and chip level.

 

EXPERIENCE REQUIREMENTS:

  • Proficient in SoC/IP integration, Synthesis, STA checks and SoC FEINT flows.
  • 6+ years of hands-on RTL design synthesis and integration experience in ASIC product development.
  • Strong RTL design experience.
  • Proficient in System Verilog, Understanding of UVM test benches and scripting languages (csh, perl, Python, etc.).
  • Proficient in SoC level timing closure, LEC failure debugging, understanding of Synthesis, lint and CDC flows/tools.
  • Need to mentor junior engineers and take IP leadership role within SoC groups.

 

ACADEMIC CREDENTIALS: 

  • Bachelors or Masters degree in computer engineering/Electrical Engineering 
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