MTS Silicon Design Engineer ( Analog Mixed Signal Layout Engineer with 10+yrs )

Oct 21, 2024
Hyderabad, India
... Not specified
... Intermediate
Full time
... Office work


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MTS SILICON DESIGN ENGINEER 

 

Master’s/Bachelor’s Degree in Electrical/Electronics engineering with more than 10 years of experience in Analog Mixed Signal Layout. Successful candidate would be responsible for layout in advanced CMOS technologies including floorplan, placement, routing, DRC, LVS, EMIR etc. You should have worked on FinFet technology nodes on various analog mixed signal blocks such as PLL, Bandgap, ADC, DAC, SERDES, IO etc. together with fullchip integration of few devices. Engineer should be well versed with tools such as Virtuoso/XL/GXL/EXL, IC23.1, Calibre etc. You are required to work with circuit designers to meet design specifications. You are also expected to provide technical guidance to junior engineers. This job requires excellent teamwork, good communication and strong problem solving skill.

 

Job Requirements:

 

  • Responsible to provide technical guidance to the team and coordination with circuit designers
  • Efficient in handling designs from across the globe
  • Responsible for independent planning and execution of layout for various designs in 3nm technology node and below
  • Hands on experience in all stages of the design such as Floorplanning, Placement, Layout, Physical Verification etc.
  • Strong debug capabilities with parasitic extraction, LVS/DRC and other Physical verification checks
  • Good command over EMIR tools like Totem, Redhawk etc.
  • Knowledge of scripting languages like SKILL, PERL, TCL etc. is desirable
  • Strong problem solving skills
  • Excellent communication skills
  • Sound knowledge of device matching, pitch matching, double patterning and other Layout Dependent Effects
  • Sound knowledge of pads arrangements and ESD/Latch-up requirements

 

#LI-SR4




Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

MTS SILICON DESIGN ENGINEER 

 

Master’s/Bachelor’s Degree in Electrical/Electronics engineering with more than 10 years of experience in Analog Mixed Signal Layout. Successful candidate would be responsible for layout in advanced CMOS technologies including floorplan, placement, routing, DRC, LVS, EMIR etc. You should have worked on FinFet technology nodes on various analog mixed signal blocks such as PLL, Bandgap, ADC, DAC, SERDES, IO etc. together with fullchip integration of few devices. Engineer should be well versed with tools such as Virtuoso/XL/GXL/EXL, IC23.1, Calibre etc. You are required to work with circuit designers to meet design specifications. You are also expected to provide technical guidance to junior engineers. This job requires excellent teamwork, good communication and strong problem solving skill.

 

Job Requirements:

 

  • Responsible to provide technical guidance to the team and coordination with circuit designers
  • Efficient in handling designs from across the globe
  • Responsible for independent planning and execution of layout for various designs in 3nm technology node and below
  • Hands on experience in all stages of the design such as Floorplanning, Placement, Layout, Physical Verification etc.
  • Strong debug capabilities with parasitic extraction, LVS/DRC and other Physical verification checks
  • Good command over EMIR tools like Totem, Redhawk etc.
  • Knowledge of scripting languages like SKILL, PERL, TCL etc. is desirable
  • Strong problem solving skills
  • Excellent communication skills
  • Sound knowledge of device matching, pitch matching, double patterning and other Layout Dependent Effects
  • Sound knowledge of pads arrangements and ESD/Latch-up requirements

 

#LI-SR4

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