PMTS Silicon Design Engineer

Mar 07, 2024
Shanghai, China
... Not specified
... Intermediate
Full time
... Office work


WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

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SMTS/PMTS IP design verification

 

THE ROLE:

The role will work in an IP team as a senior engineer individual contributor or as a technical leader, who will work with IP Arch/designer/other DV to verify IP quality and deliver to upper level environments. The role also need to work cross IP/soc team for communication, alignment and co-work to deliver successful productions to customers.

 

THE PERSON:

The candidate is preferred to be PhD with minimum of 8 years, MSEE with minimum of 10 years, or BSEE with minimum of 12 years experience in digital ASIC/SOC design verification.  The candidate should have strong experience on ASIC/SOC design and verification flow.

 

KEY RESPONSIBILITIES:

  • The successful candidate will apply current functional verification techniques to perform and improve pre-silicon IP verification quality and product Time to Market for ASIC/SOC design. 
  • The candidate would involve technically in the porting/creation of the DV environment for the new design, block and IP level test plan creation and implementation, coverage analysis, and regression cleanup.
  •  PMTS candidate should be able to work independently on new domain and deploy new methodology to wider range, driving a system task cross teams.

 

PREFERRED EXPERIENCE:

  • Digital IP verification with SV/UVM/Formal Verification or new methodology of the industry.
  • Simulation model creation and testbench build (better with UVM).
  • Innovation for better quality/efficiency.
  • Good logical thinking and expression. Can describe a technical issue/topic to audience not familiar with it.
  • Good cooperation and influence cross teams.
  • It’s a plus if have one or more of the following experience/knowledge, such as X86/ARM/8051 architecture, AMBA(AXI/AHB/APB) bus, PCIe protocol.
  • It’s a plus if have f/w writing and debug experience or experience to co-work with f/w team for f/w sequence define in embedded design.
  • It’s a plus to be good at some script language, such as Perl, python. Or some database experience (for IP technical info maintain).
  • It’s also a plus if have experience focusing on SV assertion/coverage/formal verification.

 

 

ACADEMIC CREDENTIALS:

  • The candidate is preferred to be PhD with minimum of 8 years, MSEE with minimum of 10 years, or BSEE with minimum of 12 years experience in digital ASIC/SOC design verification. 

 

LOCATION:

Shanghai,Beijing

 

#LI-JG2

#HYBRID




Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

SMTS/PMTS IP design verification

 

THE ROLE:

The role will work in an IP team as a senior engineer individual contributor or as a technical leader, who will work with IP Arch/designer/other DV to verify IP quality and deliver to upper level environments. The role also need to work cross IP/soc team for communication, alignment and co-work to deliver successful productions to customers.

 

THE PERSON:

The candidate is preferred to be PhD with minimum of 8 years, MSEE with minimum of 10 years, or BSEE with minimum of 12 years experience in digital ASIC/SOC design verification.  The candidate should have strong experience on ASIC/SOC design and verification flow.

 

KEY RESPONSIBILITIES:

  • The successful candidate will apply current functional verification techniques to perform and improve pre-silicon IP verification quality and product Time to Market for ASIC/SOC design. 
  • The candidate would involve technically in the porting/creation of the DV environment for the new design, block and IP level test plan creation and implementation, coverage analysis, and regression cleanup.
  •  PMTS candidate should be able to work independently on new domain and deploy new methodology to wider range, driving a system task cross teams.

 

PREFERRED EXPERIENCE:

  • Digital IP verification with SV/UVM/Formal Verification or new methodology of the industry.
  • Simulation model creation and testbench build (better with UVM).
  • Innovation for better quality/efficiency.
  • Good logical thinking and expression. Can describe a technical issue/topic to audience not familiar with it.
  • Good cooperation and influence cross teams.
  • It’s a plus if have one or more of the following experience/knowledge, such as X86/ARM/8051 architecture, AMBA(AXI/AHB/APB) bus, PCIe protocol.
  • It’s a plus if have f/w writing and debug experience or experience to co-work with f/w team for f/w sequence define in embedded design.
  • It’s a plus to be good at some script language, such as Perl, python. Or some database experience (for IP technical info maintain).
  • It’s also a plus if have experience focusing on SV assertion/coverage/formal verification.

 

 

ACADEMIC CREDENTIALS:

  • The candidate is preferred to be PhD with minimum of 8 years, MSEE with minimum of 10 years, or BSEE with minimum of 12 years experience in digital ASIC/SOC design verification. 

 

LOCATION:

Shanghai,Beijing

 

#LI-JG2

#HYBRID

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