RTL Design Engineer 11+ years

Aug 29, 2024
Bengaluru, India
... Not specified
... Intermediate
Full time
... Office work


WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_




SMTS SILICON DESIGN ENGINEER

THE ROLE:

  • As an experienced engineer in the RTL design team of the IDC Cores engineering group.
  • Your expertise in RTL design and coding will enable AMD to meet key goals such as power, performance, and area targets.
  • You will collaborate closely with a team of design engineers on a significant project in the early stages.
  • Execute on RTL design and coding for various sections of a given CPU features, microprocessor pipeline,  and related logic to develop great technology
  • Collaborate with other teams assisting with design verification, synthesis, power reduction, timing convergence, and floor planning to realize a great design

PREFERRED SKILLS:

Ideally you bring the following experience and attributes to our team:

  • Experience in high-performance microprocessor design and microarchitecture
  • Should have worked on high frequency, power-optimized Silicon designs in his/her career
  • Verilog RTL development experience using industry tools in a CPU, SOC or ASIC environment such that you demonstrate strong facility with:
    • Microprocessor architecture
    • Logic design
    • RTL coding experience for a high-speed processor
    • Power saving techniques
    • Strong problem solving and debugging skills
    • Your commitment to innovating as a team as shown through excellent communication, knowledge of proper documentation techniques, and a track record of independently driving tasks to completion
    • Breadth as well as depth as evidenced by exposure to physical design and verification methods and awareness of synthesis, place and route, and timing closure concepts

ADDITIONAL EXPERIENCE DESIRED:

  • Background in other aspects of ASIC implementation, especially with synthesis flow, static timing analysis (STA), and power flow (PTPX) will be a plus.
  • Knowledge of microprocessor design-for-test (DFT) and design-for-debug (DFD) logic will be a plus.
  • Experience in clocking, reset, power-up sequences and power management
  • Experience with x86 architecture,  ARM or any other industry standard microprocessor ISA.
  • Scripting experience such as Perl, shell, and Tcl
  • Working knowledge of C/C++/System Verilog/UVM with verif background will be a plus.

ACADEMIC CREDENTIALS:

Master’s degree preferred with emphasis in Electrical/Electronics Engineering, Computer Engineering, or Computer Science with a focus on computer architecture

 

#LI-ST1




Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

SMTS SILICON DESIGN ENGINEER

THE ROLE:

  • As an experienced engineer in the RTL design team of the IDC Cores engineering group.
  • Your expertise in RTL design and coding will enable AMD to meet key goals such as power, performance, and area targets.
  • You will collaborate closely with a team of design engineers on a significant project in the early stages.
  • Execute on RTL design and coding for various sections of a given CPU features, microprocessor pipeline,  and related logic to develop great technology
  • Collaborate with other teams assisting with design verification, synthesis, power reduction, timing convergence, and floor planning to realize a great design

PREFERRED SKILLS:

Ideally you bring the following experience and attributes to our team:

  • Experience in high-performance microprocessor design and microarchitecture
  • Should have worked on high frequency, power-optimized Silicon designs in his/her career
  • Verilog RTL development experience using industry tools in a CPU, SOC or ASIC environment such that you demonstrate strong facility with:
    • Microprocessor architecture
    • Logic design
    • RTL coding experience for a high-speed processor
    • Power saving techniques
    • Strong problem solving and debugging skills
    • Your commitment to innovating as a team as shown through excellent communication, knowledge of proper documentation techniques, and a track record of independently driving tasks to completion
    • Breadth as well as depth as evidenced by exposure to physical design and verification methods and awareness of synthesis, place and route, and timing closure concepts

ADDITIONAL EXPERIENCE DESIRED:

  • Background in other aspects of ASIC implementation, especially with synthesis flow, static timing analysis (STA), and power flow (PTPX) will be a plus.
  • Knowledge of microprocessor design-for-test (DFT) and design-for-debug (DFD) logic will be a plus.
  • Experience in clocking, reset, power-up sequences and power management
  • Experience with x86 architecture,  ARM or any other industry standard microprocessor ISA.
  • Scripting experience such as Perl, shell, and Tcl
  • Working knowledge of C/C++/System Verilog/UVM with verif background will be a plus.

ACADEMIC CREDENTIALS:

Master’s degree preferred with emphasis in Electrical/Electronics Engineering, Computer Engineering, or Computer Science with a focus on computer architecture

 

#LI-ST1

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