RTL Design Engineer

Sep 13, 2023
San Jose, United States
... Not specified
... Intermediate
Full time
... Office work


WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_




THE ROLE: 

This role focuses on micro-architecture, RTL design and validation of high-speed interfaces such as Chip-to-Chip interconnect and highly configurable mufti-protocol PHYs. Be a part of the definition, design, and development of industry-leading interface IP. The design engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career.

THE PERSON: 

You have a passion for digital design, and verification in general.  You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. 

 

KEY RESPONSIBILITIES:

  • Participate in IP architecture definition.
  • Perform RTL design, including micro-architecture definition of the digital portions of the IP and drive for optimum power, performance, and area.
  • Work closely with functional verification team to meet coverage and quality standards. 
  • Setup CDC checks, analyze and resolve CDC issues in the design.
  • Work closely with methodology and PD teams to implement RTL design into GDSII.
  • Support IP integration into AMD SOCs/FPGAs
  • Work with IP lead, system architects, IC designers and physical designers to guarantee quality/timely deliverables meeting project’s schedule and technical requirements.
  • Support post-silicon product bring-up/debug and sign-off on test-plans and characterization reports.

 

PREFERRED EXPERIENCE: 

  • Proven track record of on-time IP delivery to SOC and successfully taking designs to production.
  • Demonstrated proficiency in some or all the following areas:
    • SerDes/Memory/Chip-to-Chip interconnect PHY Designs.
    • Design of digital circuits and components using Verilog/System Verilog
    • Debugging in digital and mixed-signal simulation environment.
    • Power-optimization of digital designs. 
    • Multi-clock domain designs.
    • Design constraints for synthesis and  static timing analysis.
    • Logic synthesis, timing closure, logical equivalence checking and ECOs.
    • Scripting languages such as Perl, Tcl, or Python. 
    • Collaboration with verification, DFT and physical design teams. 
    • DFT design and methodologies especially for Logic BIST.
  • Excellent verbal, and interpersonal communication skills.
  • Excellent technical communications. Ability to produce technical documentation.
  • Able to operate with minimum direct supervision but also work cross-functionally, cross-geographies in a dynamic fast paced environment.
  • Exhibit strong initiative and ownership of tasks and responsibilities. Seek help proactively as well as share and pass on knowledge.

 

ACADEMIC CREDENTIALS: 

  •  
  • BS/MS EE and 5/7+ yrs. experience designing high-speed Physical layer IP  for high performance, low power FPGA/SOC.

 

LOCATION:
San Jose, CA

 

 

 

#LI-TB2




At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

THE ROLE: 

This role focuses on micro-architecture, RTL design and validation of high-speed interfaces such as Chip-to-Chip interconnect and highly configurable mufti-protocol PHYs. Be a part of the definition, design, and development of industry-leading interface IP. The design engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career.

THE PERSON: 

You have a passion for digital design, and verification in general.  You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. 

 

KEY RESPONSIBILITIES:

  • Participate in IP architecture definition.
  • Perform RTL design, including micro-architecture definition of the digital portions of the IP and drive for optimum power, performance, and area.
  • Work closely with functional verification team to meet coverage and quality standards. 
  • Setup CDC checks, analyze and resolve CDC issues in the design.
  • Work closely with methodology and PD teams to implement RTL design into GDSII.
  • Support IP integration into AMD SOCs/FPGAs
  • Work with IP lead, system architects, IC designers and physical designers to guarantee quality/timely deliverables meeting project’s schedule and technical requirements.
  • Support post-silicon product bring-up/debug and sign-off on test-plans and characterization reports.

 

PREFERRED EXPERIENCE: 

  • Proven track record of on-time IP delivery to SOC and successfully taking designs to production.
  • Demonstrated proficiency in some or all the following areas:
    • SerDes/Memory/Chip-to-Chip interconnect PHY Designs.
    • Design of digital circuits and components using Verilog/System Verilog
    • Debugging in digital and mixed-signal simulation environment.
    • Power-optimization of digital designs. 
    • Multi-clock domain designs.
    • Design constraints for synthesis and  static timing analysis.
    • Logic synthesis, timing closure, logical equivalence checking and ECOs.
    • Scripting languages such as Perl, Tcl, or Python. 
    • Collaboration with verification, DFT and physical design teams. 
    • DFT design and methodologies especially for Logic BIST.
  • Excellent verbal, and interpersonal communication skills.
  • Excellent technical communications. Ability to produce technical documentation.
  • Able to operate with minimum direct supervision but also work cross-functionally, cross-geographies in a dynamic fast paced environment.
  • Exhibit strong initiative and ownership of tasks and responsibilities. Seek help proactively as well as share and pass on knowledge.

 

ACADEMIC CREDENTIALS: 

  •  
  • BS/MS EE and 5/7+ yrs. experience designing high-speed Physical layer IP  for high performance, low power FPGA/SOC.

 

LOCATION:
San Jose, CA

 

 

 

#LI-TB2

COMPANY JOBS
1236 available jobs
WEBSITE
Top Jobs