WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_

SMTS SILICON DESIGN ENGINEER

THE ROLE: 

Work with global physical design team for large scale ASIC chip physical implementation.Focus on physical design of deep sub-micron GPU chips including block level  floor planning, fullchip timing closure, place&route, physical verification etc

THE PERSON:  

The individual is expected to be an expert in multiple aspects in PD areas and provide technically leadership to the engineering team. The individual is also expected to be accountable for project delivery.

KEY RESPONSIBILITIES:  

• Work with global Front-End design team and physical design team for large scale ASIC chip physical implementation.
• Work with methodology team for advanced PPA improvements.

PREFERRED EXPERIENCE:  

• 8+ years or more years of experience in physical design of deep submicron digital ASIC chips
• Good listening, writing and speaking English
• Familiar with Back-End (physical design) EDA tools and hierarchical fullchip floorplan flow
• Good at scripts with perl/phthon/tcl
• Plus with 3+ projects tapeout experience

ACADEMIC CREDENTIALS:  

• MSEE with 10+ years or Bachelor with 12+ years of industrial experience in ASIC design

LOCATION:

Shanghai

#LI-VC1

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

SMTS SILICON DESIGN ENGINEER

THE ROLE: 

Work with global physical design team for large scale ASIC chip physical implementation.Focus on physical design of deep sub-micron GPU chips including block level  floor planning, fullchip timing closure, place&route, physical verification etc

THE PERSON:  

The individual is expected to be an expert in multiple aspects in PD areas and provide technically leadership to the engineering team. The individual is also expected to be accountable for project delivery.

KEY RESPONSIBILITIES:  

• Work with global Front-End design team and physical design team for large scale ASIC chip physical implementation.
• Work with methodology team for advanced PPA improvements.

PREFERRED EXPERIENCE:  

• 8+ years or more years of experience in physical design of deep submicron digital ASIC chips
• Good listening, writing and speaking English
• Familiar with Back-End (physical design) EDA tools and hierarchical fullchip floorplan flow
• Good at scripts with perl/phthon/tcl
• Plus with 3+ projects tapeout experience

ACADEMIC CREDENTIALS:  

• MSEE with 10+ years or Bachelor with 12+ years of industrial experience in ASIC design

LOCATION:

Shanghai

#LI-VC1